Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

Abstract: A display assembly with dielectric filters is presented herein. The display assembly includes a light source assembly, a dielectric filter array, and a modulation layer. The light source assembly generates laser light in multiple color channels, and each color channel is associated with a different laser emission spectrum. The dielectric filter array includes respective sets of reflective dielectric filters for each color channel. Each set of reflective dielectric filters is matched to the different laser emission spectrum such that reflective dielectric filters in each set transmit light in the different laser emission spectrum and reflect light outside of the different laser emission spectrum. The modulation layer is positioned between a first electrode layer patterned on the dielectric filter array and a second electrode layer. The modulation layer modulates light from the dielectric filter array based on emission instructions applied via the first and second electrode layers to form an image.

Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.

Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

Abstract: A touch sensor panel comprising a first touch node electrode of a plurality of touch node electrodes, the first touch node electrode coupled to a first sense connection comprising a first set of traces, the first sense connection configured to have a first resistance per unit length that varies along a length of the first sense connection, and a second touch node electrode of the plurality of touch node electrodes, the second touch node electrode coupled to a second sense connection comprising a second set of traces, the second sense connection configured to have a second resistance per unit length that varies along a length of the second sense connection differently than the first resistance per unit length varies along the length of the first sense connection. An effective resistance of the first sense connection and the second sense connection are equal.

Abstract: The disclosure is related to head-to-head (H2H) gate on arrays (GOA) for pixel-based displays that may have reduced dimensions. In the described embodiments, the H2H design with alternate logic may be used to drive groups of pixels (e.g., a pixel row or column) with a primary and a secondary driver, located in opposite ends of the bezel of the electronic device. In the alternate-logic design, a shared shift-register may be used to enable two rows or columns. Embodiments in which more than two rows or columns are controlled by a single shift register are also described.

Abstract: The disclosure is related to head-to-head (H2H) gate on arrays (GOA) for pixel-based displays that may have reduced dimensions. In the described embodiments, the H2H design with alternate logic may be used to drive groups of pixels (e.g., a pixel row or column) with a primary and a secondary driver, located in opposite ends of the bezel of the electronic device. In the alternate-logic design, a shared shift-register may be used to enable two rows or columns. Embodiments in which more than two rows or columns are controlled by a single shift register are also described.

Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

Abstract: A touch sensor panel comprising a first touch node electrode of a plurality of touch node electrodes, the first touch node electrode coupled to a first sense connection comprising a first set of traces, the first sense connection configured to have a first resistance per unit length that varies along a length of the first sense connection, and a second touch node electrode of the plurality of touch node electrodes, the second touch node electrode coupled to a second sense connection comprising a second set of traces, the second sense connection configured to have a second resistance per unit length that varies along a length of the second sense connection differently than the first resistance per unit length varies along the length of the first sense connection. An effective resistance of the first sense connection and the second sense connection are equal.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.