Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: A method for manufacturing a CMOS device includes: forming a gate structure and gate sidewalls of the CMOS device, wherein the material of the gate sidewalls is silicon nitride; depositing a silicon nitride film directly on the gate structure and the gate sidewalls, wherein the depositing is performed via atomic layer deposition (ALD); and performing a photolithography process to define an ion implantation region.

Abstract: A method of forming a strained semiconductor device includes: forming a substrate and a MOS device on the substrate; depositing a molecular plug film structure on the MOS device, The molecular plug film structure includes at least one molecular plug film, depositing a stress film on the molecular plug film structure, and performing an annealing process. The stress applied to the MOS device by the stress film is increased by the annealing process. The structure made by the method includes: a MOS device formed on a substrate, a molecular plug film structure formed on the MOS device, the molecular plug film structure includes at least one molecular plug film, and a stress film formed on the molecular plug film structure.

Abstract: An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 ?; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

Abstract: An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 ?; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: A method of forming a strained semiconductor device includes: forming a substrate and a MOS device on the substrate; depositing a molecular plug film structure on the MOS device, The molecular plug film structure includes at least one molecular plug film, depositing a stress film on the molecular plug film structure, and performing an annealing process. The stress applied to the MOS device by the stress film is increased by the annealing process. The structure made by the method includes: a MOS device formed on a substrate, a molecular plug film structure formed on the MOS device, the molecular plug film structure includes at least one molecular plug film, and a stress film formed on the molecular plug film structure.

Abstract: A method for manufacturing a CMOS device includes: forming a gate structure and gate sidewalls of the CMOS device, wherein the material of the gate sidewalls is silicon nitride; depositing a silicon nitride film directly on the gate structure and the gate sidewalls, wherein the depositing is performed via atomic layer deposition (ALD); and performing a photolithography process to define an ion implantation region.

Abstract: The present disclosure provides an electric fuse structure and a manufacturing method therefor, the manufacturing method including providing a substrate, forming a polysilicon corresponding to the electric fuse structure on the substrate, performing a source-drain ion implantation of a first doping type on the polysilicon, performing a source-drain ion implantation of a second doping type on the polysilicon, the first doping type being different from the second doping type, and forming a metal salicide on the surface of the doped polysilicon. The electric fuse structure manufactured according to the manufacturing method provided in the present disclosure has a high post-value resistance, so that a programming current window is effectively optimized, and the manufactured electric fuse structure has a uniform internal interface and good electrical characteristics.

Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.

Abstract: The present disclosure provides an electric fuse structure and a manufacturing method therefor, the manufacturing method including providing a substrate, forming a polysilicon corresponding to the electric fuse structure on the substrate, performing a source-drain ion implantation of a first doping type on the polysilicon, performing a source-drain ion implantation of a second doping type on the polysilicon, the first doping type being different from the second doping type, and forming a metal salicide on the surface of the doped polysilicon. The electric fuse structure manufactured according to the manufacturing method provided in the present disclosure has a high post-value resistance, so that a programming current window is effectively optimized, and the manufactured electric fuse structure has a uniform internal interface and good electrical characteristics.

Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.

Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.

Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.

Abstract: A method of manufacturing a fin field effect transistor is provided. A double spacer protective layer comprising an outer spacer (the first spacer) and an inner spacer (the second spacer) is formed on both sides of the gate, and the thickness of the outer spacer can be adjusted to accurately control the distance between the source/drain ion implantation area and the channel, so as to solve the problem of the hot carrier injection effect caused by the distance being too close between the channel and the source/drain area; in addition, the outer spacers and the inner spacers can be formed by only two film deposition and etching processes without adding a photolithography mask, which can effectively prevent the contact between the gate and the source/drain, so as to substantially reduce the parasitic capacitance.

Abstract: The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.

Abstract: The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.

Abstract: A fluxless reflow process for bump formation is provided, which includes: a purifying process for keeping solder in a state of melting or half-melting for 40 s to 540 s; a ball-forming process for melting the solder completely to form ball-like bumps; and a cooling process. The splashing of solder can be avoided and the defect that there may be solder balls around the bumps can be eliminated.