Abstract: A semiconductor structure includes a substrate, first transistor columns and second transistor columns on the substrate. The first transistor columns and the second transistor columns are alternately arranged. A first transistor column includes a plurality of first transistors arranged in a first direction. A second transistor column includes a plurality of second transistors arranged in the first directions. The plurality of first transistors in the first transistor column are electrically connected to the plurality of second transistors in the second transistor column in one-to-one correspondence. A length direction of the first transistor is the same as a length direction of the second transistor. A center of the first transistor is offset from a center of the second transistor in the first direction.

Abstract: Disclosed in the embodiments of the disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure includes: a substrate; a plurality of grooves, located in the substrate and extending in a first direction; a plurality of word line structures, located in the grooves; and a plurality of semiconductor layers, each at least partially located between a word line structure and an inner wall of a groove. The semiconductor layer includes oxide semiconductor material.

Abstract: Embodiment relates to a semiconductor structure and a fabrication method thereof. The method for fabricating a semiconductor structure includes: providing a substrate including an array region and a peripheral region connected to the array region; arranging a plurality of pads on the array region, an isolation trench being formed between adjacent two of the plurality of pads; and forming a to-be-etched path layer on a sidewall of the isolation trench. In the method for fabricating a semiconductor structure, after the plurality of pads are formed, a to-be-etched path layer is formed on a sidewall of the isolation trench between the plurality of pads. The to-be-etched path layer may be in contact with a to-be-etched material layer in the array region. After a flat surface is formed on the array region and the peripheral region, the to-be-etched path layer and the to-be-etched material layer may be removed in sequence.

Abstract: The present disclosure relates to the technical field of semiconductors, and mainly relates to a memory, a semiconductor structure, and a manufacturing method thereof. The manufacturing method of the present disclosure includes: providing a substrate, where the substrate includes an array region and a peripheral region, an isolation layer, a conductive contact plug, and a plurality of bit line structures spaced from each other are formed in the array region, the isolation layer covers sidewalls of the bit line structures, the conductive contact plug is formed in a region surrounded by the isolation layer between adjacent bit line structures, and a stacked film layer is formed in the peripheral region; forming a mask layer covering the bit line structures, the isolation layer, the conductive contact plug, and the stacked film layer; and etching the mask layer to expose a top of the isolation layer.

Abstract: A method for manufacturing a semiconductor structure includes: forming multiple trenches spaced apart from each other and extending in a first direction in a substrate, and forming a first insulating layer on sidewalls and bottoms of the trenches; forming a first conductive layer on a surface of the first insulating layer; removing part of the first conductive layer to an initial depth by a first etching process; removing remaining part of the first conductive layer to a target depth by a second etching process.

Abstract: A method for processing a semiconductor structure and a method for forming a word line structure are provided. The method for processing the semiconductor structure includes: providing a semiconductor structure including a groove and a metal layer located in the groove, where an edge position of a top surface of the metal layer is higher than a center position of the top surface of the metal layer; enabling the semiconductor structure to be in a rotating state; and performing at least one metal surface planarization process on the semiconductor structure, so that the top surface of the metal layer after being processed is more planar than the top surface of the metal layer before being processed. Each of the at least one metal surface planarization process includes: etching the top surface of the metal layer by a first reagent; and cleaning the semiconductor structure by a second reagent.