Abstract: A semiconductor device includes a drain, a substrate, an epitaxial layer, and a semiconductor layer. The semiconductor layer includes a source region located on a side the semiconductor layer away from the epitaxial layer. A trench extending to the epitaxial layer is disposed on a side of the source region is away from the epitaxial layer. A gate, an electrode plate, a first shield gate, and a second shield gate are disposed in the trench. The electrode plate is located between the first shield gate and the second shield gate. The trench is further filled with an oxidized layer structure. The first shield gate and the second shield gate are separately spaced from the electrode plate to form electrode plate capacitance. One of the source region, the drain, and the gate is electrically connected to the electrode plate a first electrode, and a second one of the source region, the drain, and the gate is electrically connected to the shield gate structure.

Abstract: An example SiC MOSFET includes a SiC semiconductor substrate (SSS), a drift layer on the SSS having a fin-shaped channel layer (FSCL) with a source region and a first insulated isolating layer. The FSCL does not cover the first insulated isolating layer, and the FSCL and the source region are of a stacking structure, and includes a gate electrode on the first insulated isolating layer that is separately on two sides of the stacking structure, a gate oxide layer between the gate electrode and the stacking structure, a second insulated isolating layer that covers an external side wall and an upper surface of the gate electrode, and a source electrode that covers the first insulated isolating layer, the second insulated isolating layer, and the source region. The SiC MOSFET further includes a drain electrode on a side of the SSS that is separated from the drift layer.

Abstract: A diode and a power circuit are provided. The diode may include: a first electrode layer; a drift layer located above the first electrode layer, a doping concentration of the drift layer is less than that of the first electrode layer; and the drift layer includes an active region and a terminal region surrounding the active region; a second electrode layer disposed in the active region, where the second electrode layer and the drift layer are doped with impurities of different properties; and the second electrode layer includes a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench, where the first region is connected to a power supply through a first conductor, and the second region is connected to the power supply through a second conductor, a first resistor, and the first conductor sequentially.

Abstract: A method comprises the steps of providing a semiconductor device wafer; forming a first plurality of alignment marks on a first side of the semiconductor device wafer; forming a first pattern of a first conductivity type; forming a second plurality of alignment marks on a second side of the semiconductor device wafer; forming a bonded wafer by bonding a carrier wafer to the semiconductor device wafer; forming a third plurality of alignment marks on a free side of the carrier wafer; applying a grinding process; forming a plurality of device structure members; removing the carrier wafer; applying an implanting process and an annealing process; applying a metallization process and applying a singulation process.

Abstract: A method comprises the steps of providing a semiconductor device wafer; forming a first plurality of alignment marks on a first side of the semiconductor device wafer; forming a first pattern of a first conductivity type; forming a second plurality of alignment marks on a second side of the semiconductor device wafer; forming a bonded wafer by bonding a carrier wafer to the semiconductor device wafer; forming a third plurality of alignment marks on a free side of the carrier wafer; applying a grinding process; forming a plurality of device structure members; removing the carrier wafer; applying an implanting process and an annealing process; applying a metallization process and applying a singulation process.