Abstract: The present disclosure provides a cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory (CIM) macro and method for edge intelligence. The cell includes a SRAM cell and a column-shared reconfigurable Boolean computation cell. A reconfiguration computation is performed based on the SRAM cell to obtain a reconfigured structure; the column-shared reconfigurable Boolean computation cell outputs a computation result based on the reconfigured structure; and a peripheral computation circuit supporting pipelined bit-serial addition outputs an in-memory addition result on a basis of a Boolean computation. In order to meet a requirement of edge artificial intelligence (AI) for a low power consumption and a low hardware overhead, and to enable an accelerator to adapt to a fast iterative software algorithm as much as possible.