Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which are related to a field of quantum computing. The specific implementation includes: a superconducting circuit structure, including: at least three computational qubits; a bus qubit connected to the respective computational qubits, wherein couplings between two of the computational qubits connected by the bus qubit are equivalent; and coupler qubits disposed between the respective computational qubits and the bus qubit, to connect the respective computational qubits to the bus qubits, wherein the coupler qubit is configured to regulate coupling strength between the computational qubit and the bus qubit. Couplings between any two computational qubits may be realized, so that an operation of a quantum gate between any two computational qubits is achieved, while crosstalk between computational qubits may be effectively suppressed.

Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which relate to the field of quantum computing. The superconducting circuit structure includes: at least two qubits; a connector, coupled with the two qubits respectively, to realize transversal coupling with each of the two qubits; and a coupler, coupled with the two qubits respectively, to realize longitudinal coupling with each of the two qubits. Therefore, the ?z?z parasitic coupling between the qubits is effectively removed, and a two-qubit gate with high fidelity is obtained.

Abstract: The present disclosure discloses a high-fidelity superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer, which relate to the field of quantum computation. The specific implementation is as follows: computation qubits; a coupling device configured to be coupled with two computation qubits, respectively; a connecting component disposed between a computation qubit and the coupling device to couple the computation qubit with the coupling device, so as to implement a target quantum gate based on the coupling device and the computation qubit.

Abstract: A function processing method and device, and an electronic device are provided. The function processing method includes: obtaining a first polynomial function including a plurality of terms consisting of a plurality of first variables; constructing a node route diagram of a quantum approximate optimization algorithm (QAOA) based on the first polynomial function, where the node route diagram includes K nodes, K is determined based on the first polynomial function, and K is an integer greater than 1; generating quantum entangled states of the node route diagram, where the quantum entangled states include target quantum states of the K nodes in the node route diagram; and sequentially performing a numerical measurement on each node in the K nodes based on the target quantum state of the K nodes in the node route diagram, to obtain a first target numerical measurement result of the plurality of first variables.

Abstract: A processing method for a quantum circuit, an electronic device, and a storage medium are provided, and relates to the field of quantum computing, and in particular to the field of quantum circuit compilation. The method includes: acquiring a first measurement order of respective logical qubits in the quantum circuit; determining a physical qubit order corresponding to the first measurement order based on a target mapping relationship between the respective logical qubits and respective physical qubits in a chip coupling diagram, wherein the target mapping relationship is obtained by updating based on an initial mapping relationship between the respective logical qubits and the respective physical qubits; determining a second measurement order of the respective logical qubits of the quantum circuit based on the physical qubit order and the initial mapping relationship; and measuring the quantum circuit based on the second measurement order, to obtain a measurement result.

Abstract: A digital signature method includes: obtaining a to-be-transmitted file, a private key and first compressed data, the first compressed data being obtained through compressing a symmetric tensor, the private key including a first invertible matrix; generating L pieces of second compressed data corresponding to L second symmetric tensors in accordance with the first invertible matrix and the first compressed data; creating a Hash value of a root node in a Hash tree in accordance with L pieces of created data, the L pieces of created data being the L pieces of second compressed data or the L second symmetric tensors; and generating signature information about the to-be-transmitted file for the first electronic device in accordance with the first character string, the first invertible matrix, the second invertible matrix, the L pieces of second compressed data and the Hash value of the root node in the Hash tree.

Abstract: This disclosure provides a node grouping method and apparatus and an electronic device, and relates to the field of evolutionary computing in quantum computing. The method includes: obtaining a graph of to-be-grouped nodes, wherein the graph of to-be-grouped nodes includes M first nodes; constructing a QAOA (quantum approximate optimization algorithm) node circuit graph based on the graph of to-be-grouped nodes, the node circuit graph including K nodes which including the M first nodes; generating a quantum entangled state of the node circuit graph that includes target quantum states of the K nodes in the node circuit graph; performing a group measurement on each of the K nodes sequentially based on the target quantum states of the K nodes to obtain a target group measurement result of the M first nodes; determining a grouping output result of the M first nodes based on the target group measurement result.

Abstract: Provided are a quantum pulse determining method, apparatus, device and readable storage medium, where basic pulses corresponding to basic logic gates are set in advance, the method including: when manipulating a qubit according to a quantum logic gate, splitting the quantum logic gate to obtain sub-logic gates; and searching for sub-pulses corresponding to the sub-logic gates among the basic pulses, and manipulating the qubit according to the sub-pulse. Basic pulses are set in advance in the method, apparatus, device and readable storage medium provided by the embodiments. When a qubit is to be manipulated, the quantum logic gate can be split into multiple sub-logic gates, and then sub-pulses corresponding to the sub-logic gates are searched for among the basic pulses. Thus, sub-pulses read can be used directly to manipulate the qubit, avoiding the computing power consumed in generating pulses according to the quantum logic gate, thereby improving an operation speed.

Abstract: A digital signature method, a signature information verification method, a related apparatus and an electronic device are provided. The digital signature method includes: obtaining a to-be-sent file and a private key used by a first electronic device for digital signature, the private key including a first invertible matrix; generating L second tensors based on the first invertible matrix and a first tensor, the L second tensors including the first tensor and a tensor isomorphic to the first tensor; digitally signing the to-be-sent file based on a second invertible matrix and the first tensor, to obtain a first character string; constructing a hash value of a root node of a hash tree based on the L second tensors; generating signature information of the to-be-sent file based on the first character string, the first invertible matrix, the second invertible matrix, the L second tensors and the hash value of the root node.

Abstract: A quantum circuit simulation method and device, an apparatus, and a storage medium are provided, which are related to a field of quantum simulation computation. The specific implementation is: obtaining, based on a quantum circuit containing n qubits, an n-order pure state corresponding to the quantum circuit; determining, based on the quantum circuit, a (k, k)-order gate tensor representing a quantum gate, on which a contraction processing is to be performed with the n-order state tensor; transforming the contraction processing between the n-order state tensor and the (k, k)-order gate tensor into a processing between matrices which can be expressed in a classic computer and reduce a computation amount in the classic computer, to obtain a processing result; and using the processing result as a result of the contraction processing between the n-order state tensor and the (k, k)-order gate tensor, to complete simulation of the quantum circuit.

Abstract: This application discloses a digital signature method, a signature information verification method, a related apparatus and an electronic device, and relates to the field of information security in quantum computing. The digital signature method includes: acquiring a to-be-sent file and a private key used by a first electronic device for digital signature, where the private key includes a first invertible matrix; generating, based on a randomly generated second invertible matrix and a first tensor, a second tensor isomorphic to the first tensor; using a hash function to digitally sign the to-be-sent file based on the second tensor, to obtain a first character string; generating, based on the first character string, the first invertible matrix and the second invertible matrix, signature information provided by the first electronic device for the to-be-sent file.

Abstract: The present disclosure provides superconducting circuit architecture, a superconducting quantum chip, and a superconducting quantum computer including a plurality of coupling devices. The superconducting circuit architecture includes: a first qubit and a second qubit, and a first coupling device and a second coupling device. The first coupling device is coupled to the first qubit and the second qubit through a first connector, and the second coupling device is coupled to the first qubit and the second qubit through a second connector. The frequencies of the first qubit and the second qubit are between a frequency of the first coupling device and a frequency of the second coupling device, and a nonlinear strength of the first coupling device and a nonlinear strength of the second coupling device are opposite in sign.

Abstract: The present application discloses a method and apparatus for evaluating a quantum gate in a superconducting circuit, a device and a storage medium, which relate to the field of quantum computations. The specific scheme may include: acquiring a Hamiltonian corresponding to a superconducting circuit structure, wherein the superconducting circuit structure may include computation qubits and a coupler disposed between two of the computation qubits and coupled with the two of the computation qubits respectively; performing decoupling processing for the coupler on the Hamiltonian to obtain the processed Hamiltonian representing a coupling strength between the computation qubits; and obtaining, based on the processed Hamiltonian, a first data processing rule that takes circuit parameters of the superconducting circuit structure as input parameters, wherein a degree of a difference between a target quantum gate and a theoretical quantum gate can be obtained based on the first data processing rule.

Abstract: The present disclosure discloses a high-fidelity superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer, which relate to the field of quantum computation. The specific implementation is as follows: computation qubits; a coupling device configured to be coupled with two computation qubits, respectively; a connecting component disposed between a computation qubit and the coupling device to couple the computation qubit with the coupling device, so as to implement a target quantum gate based on the coupling device and the computation qubit.

Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which are related to a field of quantum computing. The specific implementation includes: a superconducting circuit structure, including: at least three computational qubits; a bus qubit connected to the respective computational qubits, wherein couplings between two of the computational qubits connected by the bus qubit are equivalent; and coupler qubits disposed between the respective computational qubits and the bus qubit, to connect the respective computational qubits to the bus qubits, wherein the coupler qubit is configured to regulate coupling strength between the computational qubit and the bus qubit. Couplings between any two computational qubits may be realized, so that an operation of a quantum gate between any two computational qubits is achieved, while crosstalk between computational qubits may be effectively suppressed.

Abstract: Provided are a quantum pulse determining method, apparatus, device and readable storage medium, where basic pulses corresponding to basic logic gates are set in advance, the method including: when manipulating a qubit according to a quantum logic gate, splitting the quantum logic gate to obtain sub-logic gates; and searching for sub-pulses corresponding to the sub-logic gates among the basic pulses, and manipulating the qubit according to the sub-pulse. Basic pulses are set in advance in the method, apparatus, device and readable storage medium provided by the embodiments. When a qubit is to be manipulated, the quantum logic gate can be split into multiple sub-logic gates, and then sub-pulses corresponding to the sub-logic gates are searched for among the basic pulses. Thus, sub-pulses read can be used directly to manipulate the qubit, avoiding the computing power consumed in generating pulses according to the quantum logic gate, thereby improving an operation speed.

Abstract: A superconducting circuit structure, a superconducting quantum chip, and a superconducting quantum computer are provided, which relate to the field of quantum computing. The superconducting circuit structure includes: at least two qubits; a connector, coupled with the two qubits respectively, to realize transversal coupling with each of the two qubits; and a coupler, coupled with the two qubits respectively, to realize longitudinal coupling with each of the two qubits. Therefore, the ?z?z parasitic coupling between the qubits is effectively removed, and a two-qubit gate with high fidelity is obtained.