Abstract: A method for producing a semiconductor device, the method includes forming a first ferromagnetic (FM) layer using a first process type. A tunnel barrier (TB) layer having a monocrystalline structure is formed over the first FM layer and using a second process type different from the first process type. A second FM layer is formed over the TB layer using the first process type.

Abstract: A semiconductor device, includes: (a) a substrate, (b) a gate electrode, disposed on a surface of the substrate, and including a plate, orthogonal to the surface, and having openings, a longest axis of the openings is orthogonal to the surface, and (c) elements having a shape that fits in the openings, the elements (i) are orthogonal both to the surface and to the gate electrode, (ii) extend through the openings, and (iii) are surrounded by the gate electrode and spaced away from the surface, the elements including: a first section that is located on a first side of the gate electrode and serves as a source; and a second section that is located on a second side of the gate electrode and serves as a drain, the gate electrode configured to control movement of charge carriers between the source and the drain in response to an applied electrical signal.

Abstract: An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.

Abstract: An electronic device, includes (a) a semiconductor substrate, (b) a plurality of transistors formed on a first side of the semiconductor substrate, and (c) a first set of metal interconnect layers formed on the first side of the semiconductor substrate, and a second set of metal interconnect layers formed on a second side of the semiconductor substrate opposite to the first side, each of the first set and the second set of metal interconnect layers includes (i) one or more layers whose electrical resistance is in a first range of resistances, and (ii) at least one layer whose electrical resistance is in a second range of resistances, lower than the first range.

Abstract: An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.

Abstract: A package connecting first and second circuitry components includes: a semiconductor substrate, dielectric layers formed over the semiconductor substrate, first and second substrates of the first and second circuitry components, respectively, positioned side-by-side on one of the dielectric layers, first seal ring of the first circuitry component implemented in first metal layers embedded between the first substrate and a first surface of the first circuitry component, second seal ring of the second circuitry component implemented in second metal layers embedded between the second substrate and a second surface of the second circuitry component, and a third seal ring surrounds the first and second circuitry components and embedded in the dielectric layers extrinsic to the first and second metal layers and overlaying the first and second surfaces, at least a third section of the third seal ring disposed over first and second sections of the first and second seal rings, respectively.

Abstract: An electronic device includes: (i) a first chiplet including a first seal ring, which is disposed in metal layers embedded between a first surface of the first chiplet, and a first substrate of the first chiplet, (ii) a second chiplet including a second seal ring, which is disposed in metal layers embedded between a second surface of the second chiplet, and a second substrate of the second chiplet, and (iii) a third seal ring, which surrounds the first and second chiplets and is disposed in a dielectric substrate extrinsic to the metal layers and overlaying the first and second surfaces of the first and second chiplets.

Abstract: An electronic device includes: (a) a substrate having transistors formed in the substrate frontside, (b) nano-vias (NVs) formed in the substrate and configured to electrically couple at least some of the transistors at least to the substrate backside, the NVs include power NVs configured to conduct at least electrical power between the substrate backside and the transistors, and signal NVs configured to conduct data signals at least between the substrate frontside and backside, (c) frontside interconnects formed on the substrate frontside and configured to conduct the data signals between the transistors and the signal NVS, and (d) backside interconnects formed on the substrate backside and configured to conduct (i) the electrical power between the power NVs and the power terminals and (ii) the data signals between the signal NVs and the signal terminals, the power terminals and the signal terminals are disposed between the backside interconnects and a package substrate.

Abstract: Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.

Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The second IC die is mounted on the first IC die. The first IC die includes (i) a first dielectric layer having a first dielectric surface, and (ii) a first pad having a first footprint and a first pad surface, the first pad being electrically conductive and being at least partially embedded in the first dielectric layer. The second IC die includes (i) a second dielectric layer having a second dielectric surface at least partially facing the first dielectric surface, and (ii) a second pad, which is electrically conductive and is at least partially embedded in the second dielectric layer. The second pad has a second footprint, smaller than the first footprint, and a second pad surface electrically coupled to the first pad surface.

Abstract: A method for fabricating an electronic device having two or more stacked integrated circuit (IC) dies, the method includes, disposing a first IC die on a substrate. A registration error of the first IC die between (i) a first intended position of the first IC die on the substrate, and (ii) a first actual position of the first IC die on the substrate, is determined. A second IC die is stacked on the first IC die, and at least part of the registration error of the first IC die is compensated for by shifting the second IC die, from a second intended position to a second actual position.

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) and first and second electrodes. The MTJ includes: (a) a first ferromagnetic (FM) layer, configured to have a magnetic spin in a first spin direction, and retain the first spin direction while MTJ subjected to electrical current in first and second directions, (b) a second FM layer, configured to have the magnetic spin selectively altered between the first and second spin direction, in response to altering the electrical current between the first and second directions, respectively, and (c) a stack of tunnel barrier (TB) layers, having: a first TB layer disposed over the first FM layer and having a first morphological structure, and a second TB layer, disposed between the first TB layer and the second FM layer and having a second, different, morphological structure. The first and second electrodes are electrically connected to the first and second FM layers, respectively.

Abstract: An electronic device includes (i) a substrate having a first coefficient of thermal expansion (CTE), (ii) an integrated circuit (IC) die formed on the substrate and including first metal layers having a first thickness, and second metal layers having a second thickness, greater than the first thickness, the second metal layers have a second CTE, greater than the first CTE, the first and second metal layers are configured to induce, in response to an increase in a temperature of the electronic device, a first stress that acts to cause a warpage at least in the substrate, and (iii) a dielectric layer having a third CTE less than the first and second CTEs, is (a) disposed on the second metal layers, and (b) configured to induce at least in the substrate, in response to the increase in the temperature, a second stress that compensates for at least part of the warpage.

Abstract: An Integrated Circuit (IC) includes electronic circuitry, an electronic fuse (eFuse) and a protection circuit. The eFuse is configured to be selectably programmed to a logical state. The electronic circuitry is configured to read the eFuse and to operate in accordance with the logical state read from the eFuse. The eFuse has a first range of operational voltages, and the electronic circuitry has a second range of operational voltages that is broader than the first range of operational voltages. The protection circuit is configured to prevent the electronic circuitry from misreading the logical state of the eFuse due to a voltage supply to the IC falling within the second operational voltage range but outside the first operational voltage range.

Abstract: Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.

Abstract: An electronic device includes a substrate, first and second semiconductor devices, and a power supply structure. The first semiconductor device includes a first plurality of gate all-around (GAA) field effect transistors (FETs) formed over a first side of the substrate. The second semiconductor device includes a second plurality of GAA FETs formed over a second side of the substrate, opposite the first side. The power supply structure is (a) disposed at the first side, and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs through first electrical couplings disposed at the first side, and (ii) the second plurality of GAA FETs through second electrical couplings including one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side.

Abstract: Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.

Abstract: An Integrated Circuit (IC) includes an electronic circuit and reliability monitoring circuitry. The electronic circuit includes multiple electronic components. The reliability monitoring circuitry is configured to assess, during operation of the IC in a host system, one or more parameters indicative of a reliability of one or more components-of-interest, selected from among the electronic components, and to provide an output indicative of the reliability.

Abstract: A method for producing a semiconductor device, the method includes, forming, on a substrate made from a semiconductor substance, at least one bipolar junction (BJ) transistor including a first terminal connected to a first well, the first well formed in the substrate and includes a first dopant having a first dopant concentration. At least one non-BJ transistor is formed on the substrate, the non-BJ transistor includes a second terminal connected to a second well, and the second well formed in the substrate and includes a second dopant having a same polarity as the first dopant. The first dopant concentration of the BJ transistor is higher than the second dopant concentration of the non-BJ transistor.

Abstract: An Integrated Circuit (IC) includes electronic circuitry, an electronic fuse (eFuse) and a protection circuit. The eFuse is configured to be selectably programmed to a logical state. The electronic circuitry is configured to read the eFuse and to operate in accordance with the logical state read from the eFuse. The eFuse has a first range of operational voltages, and the electronic circuitry has a second range of operational voltages that is broader than the first range of operational voltages. The protection circuit is configured to prevent the electronic circuitry from misreading the logical state of the eFuse due to a voltage supply to the IC falling within the second operational voltage range but outside the first operational voltage range.