Abstract: An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.

Abstract: A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.

Abstract: A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.

Abstract: A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

Abstract: A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

Abstract: A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

Abstract: A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.