Patents by Inventor Rupal M. Parikh

Rupal M. Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111560
    Abstract: Embodiments herein relate to providing uniform servicing of workloads at a set of servers in a computer network. A platform determines and meets the performance requirements of a workload by scaling a performance capability of a group of processing units such as central processing units (CPUs) which are assigned to service the workload. This can involve increasing the power (P) state of one or more of the processing units to a highest P state in the group, so that every processing units in the group provides the same performance for a given workload. The platform can manage scaling of the processing units performance by reading a performance profile list which indicates minimum and maximum scaling points for programs that are executed to service the workload.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Subhankar Panda, Rupal M. Parikh, Gaurav Porwal, Raghavendra Nagaraj, Sagar C. Pawar, Prakash Pillai
  • Patent number: 6986023
    Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: January 10, 2006
    Assignee: Intel Corporation
    Inventors: Nigel C. Paver, William T. Maghielse, Wing K. Yu, Jianwei Liu, Anthony Jebson, Kailesh B. Bavaria, Rupal M. Parikh, Deli Deng, Mukesh Patel, Mark Fullerton, Murli Ganeshan, Stephen J. Strazdus
  • Publication number: 20040030862
    Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 12, 2004
    Inventors: Nigel C. Paver, William T. Maghielse, Wing K. Yu, Jianwei Liu, Anthony Jebson, Kailesh B. Bavaria, Rupal M. Parikh, Deli Deng, Mukesh Patel, Mark Fullerton, Murli Ganeshan, Stephen J. Strazdus