Patents by Inventor Rupal Parikh
Rupal Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250076954Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 12, 2024Publication date: March 6, 2025Inventors: Vivek GARG, Ankush VARMA, Krishnakanth SISTLA, Nikhil GUPTA, Nikethan Shivanand BALIGAR, Stephen WANG, Nilanjan PALIT, Timothy Yee-Kwong KAM, Adwait PURANDARE, Ujjwal GUPTA, Stanley CHEN, Dorit SHAPIRA, Shruthi VENUGOPAL, Suresh CHEMUDUPATI, Rupal PARIKH, Eric DEHAEMER, Pavithra SAMPATH, Phani Kumar KANDULA, Yogesh BANSAL, Dean MULLA, Michael TULANOWSKI, Stephen Paul HAAKE, Andrew HERDRICH, Ripan DAS, Nazar Syed HAIDER, Aman SEWANI
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Patent number: 12093100Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: GrantFiled: September 26, 2020Date of Patent: September 17, 2024Assignee: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Yee-Kwong Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Paul Haake, Andrew Herdrich, Ripan Das, Nazar Syed Haider, Aman Sewani
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Publication number: 20220100247Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
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Patent number: 7161999Abstract: A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system, in one embodiment, a plurality of data units may be received at a source location in a first clocked domain. To control writing of the plurality of data units from the source location to a target location in a second clocked domain, an enable signal may be detected. This enable signal may be synchronized with respect to the second clocked domain. Finally, in response to the synchronized enable signal, the plurality of data units may be transferred from the first clocked domain to the target location in the second clocked domain. The synchronization interface may comprise a data path to capture the multi-bit digital data or signal based on a control logic implementing a mechanism (e.g.Type: GrantFiled: January 2, 2002Date of Patent: January 9, 2007Assignee: Intel CorporationInventor: Rupal Parikh
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Patent number: 6954872Abstract: A semiconductor device determines whether a clocking signal intended for latching an event at the designated location is absent, and if so, information about the event that occurred in the absence of the clocking signal may be provided at the another location. The semiconductor device, in one embodiment, includes first and second clock domains capable of receiving first and second clocks, respectively. When deployed in a processor-based system, one or more interrupting events may be registered. The semiconductor device further comprises an interface to capture the interrupting events based on a control logic implementing a mechanism (e.g., a state machine) capable of remembering information associated with the interrupting events that may occur when the first clock may be temporarily absent. When the first clock restarts, a register subsequently records the information associated with the interrupting events that may have occurred.Type: GrantFiled: September 28, 2001Date of Patent: October 11, 2005Assignee: Intel CorporationInventor: Rupal Parikh
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Publication number: 20030123588Abstract: A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system, in one embodiment, a plurality of data units may be received at a source location in a first clocked domain. To control writing of the plurality of data units from the source location to a target location in a second clocked domain, an enable signal may be detected. This enable signal may be synchronized with respect to the second clocked domain. Finally, in response to the synchronized enable signal, the plurality of data units may be transferred from the first clocked domain to the target location in the second clocked domain. The synchronization interface may comprise a data path to capture the multi-bit digital data or signal based on a control logic implementing a mechanism (e.g.Type: ApplicationFiled: January 2, 2002Publication date: July 3, 2003Inventor: Rupal Parikh
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Publication number: 20030065964Abstract: A semiconductor device determines whether a clocking signal intended for latching an event at the designated location is absent, and if so, information about the event that occurred in the absence of the clocking signal may be provided at the another location. The semiconductor device, in one embodiment, includes first and second clock domains capable of receiving first and second clocks, respectively. When deployed in a processor-based system, one or more interrupting events may be registered. The semiconductor device further comprises an interface to capture the interrupting events based on a control logic implementing a mechanism (e.g., a state machine) capable of remembering information associated with the interrupting events that may occur when the first clock may be temporarily absent. When the first clock restarts, a register subsequently records the information associated with the interrupting events that may have occurred.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Rupal Parikh