Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract: A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

Abstract: A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

Abstract: The inventive mechanism operates to optimize program efficiency in a two phase process. In the first phase, the mechanism conducts a dependency analysis on the instructions to determine dependency relationships between the various instructions in an instruction window. The mechanism thereby identifies candidates for register renaming and instruction speculation, and provisionally performs the renaming and speculation operations, while preserving information which is preferably used to reverse these operations in the second phase if it is determined that the operations may be effectively rescheduled. In the second phase, the mechanism determines whether the optimizing operations, renaming and speculation, were beneficial in each case. Each instruction for which the mechanism finds the optimizing operation to be beneficial will generally remain in optimized form. Optimizing operations found not be beneficial are generally reversed by the mechanism.

Abstract: The invention determines whether any asynchronous signals are pending and then delivers any such pending signals to the emulated application before the control is transferred to the operating system. A first mechanism sets a global flag, and checks to determine if any signals are pending. If there are pending signals, the emulator halts the emulation of the system call, and delivers the signal to the emulated application. A second mechanism handles signals that arrive after the first mechanism has performed its check. This mechanism checks to see if the global flag is set when a signal arrives. If the flag is set, then the signal is delivered immediately. If the flag is not set, then the signal is deferred. A third mechanism establishes a watch state at the beginning of the emulation, which would be changed by any action of the operating system. When a signal comes in, the emulator checks the watch state. If it does not exist, then the emulator defers the system call.