Patents by Inventor Rupesh Khare
Rupesh Khare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11668738Abstract: Circuitry for detecting a capacitive load coupled between a first node and a second node, the circuitry comprising: drive circuitry for applying a first voltage to a first node over a first time period; processing circuitry configured to: measure a second voltage at the first node; and determine that the load is a capacitive load based on the second voltage.Type: GrantFiled: June 22, 2021Date of Patent: June 6, 2023Assignee: Cirrus Logic, Inc.Inventors: Mehul Mistry, Rupesh Khare, Jack Fuller
-
Publication number: 20220404407Abstract: Circuitry for detecting a capacitive load coupled between a first node and a second node, the circuitry comprising: drive circuitry for applying a first voltage to a first node over a first time period; processing circuitry configured to: measure a second voltage at the first node; and determine that the load is a capacitive load based on the second voltage.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Mehul MISTRY, Rupesh KHARE, Jack FULLER
-
Patent number: 11522528Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.Type: GrantFiled: November 2, 2020Date of Patent: December 6, 2022Assignee: Cirrus Logic, Inc.Inventors: Gary Robertson, Hamed Sadati, Rupesh Khare, Sameer Baveja
-
Publication number: 20210075404Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.Type: ApplicationFiled: November 2, 2020Publication date: March 11, 2021Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Gary ROBERTSON, Hamed SADATI, Rupesh KHARE, Sameer BAVEJA
-
Patent number: 10856073Abstract: This application relates to switch arrangements, in particular switch arrangements suitable for switchable connecting nodes of audio driving circuitry (100) that may, in use, experience a signal swing depending on an output audio driving signal (VD). A switch arrangement (300) comprises first and second transistors (301 and 302) of the same polarity type connected in series between the first and second nodes, with a third transistor (303) connected between a defined voltage (VS) and an intermediate node (N3) between the first and second transistors. The first transistor (301) has a drain connection to the first node (N1) and a source connection to the intermediate node (N3). The second transistor (302) has a drain connection to the second node (N2) and a source connection to the intermediate node (N3).Type: GrantFiled: December 10, 2019Date of Patent: December 1, 2020Assignee: Cirrus Logic, Inc.Inventors: Rupesh Khare, Simon Foster
-
Patent number: 10855258Abstract: This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance.Type: GrantFiled: October 7, 2019Date of Patent: December 1, 2020Assignee: Cirrus Logic, Inc.Inventors: Gary Robertson, Hamed Sadati, Rupesh Khare, Sameer Baveja
-
Publication number: 20200186918Abstract: This application relates to switch arrangements, in particular switch arrangements suitable for switchable connecting nodes of audio driving circuitry (100) that may, in use, experience a signal swing depending on an output audio driving signal (VD). A switch arrangement (300) comprises first and second transistors (301 and 302) of the same polarity type connected in series between the first and second nodes, with a third transistor (303) connected between a defined voltage (VS) and an intermediate node (N3) between the first and second transistors. The first transistor (301) has a drain connection to the first node (N1) and a source connection to the intermediate node (N3). The second transistor (302) has a drain connection to the second node (N2) and a source connection to the intermediate node (N3).Type: ApplicationFiled: December 10, 2019Publication date: June 11, 2020Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Rupesh KHARE, Simon FOSTER
-
Patent number: 10142721Abstract: This application describes methods and apparatus for selectively clamping a signal path (106) for an analog audio signal to a clamp voltage, e.g. ground. Voltage clamping circuitry (200) is disclosed having a first switching device (201) in series with a second switching device (202) between a node of the signal path and the clamp voltage. The clamping circuitry is configured to be operable in: a first state where the first and second switching devices are both on to electrically connect the signal path to the clamp voltage; and also a second state to electrically disconnect the signal path from the clamp voltage. In the second state one of the first and second switching devices is configured to block conduction when the voltage at said node of the signal path is positive and the other switching device is configured to block conduction when the voltage at said node of the signal path is negative.Type: GrantFiled: February 22, 2017Date of Patent: November 27, 2018Assignee: Cirrus Logic, Inc.Inventor: Rupesh Khare
-
Publication number: 20170251294Abstract: This application describes methods and apparatus for selectively clamping a signal path (106) for an analogue audio signal to a clamp voltage, e.g. ground. Voltage clamping circuitry (200) is disclosed having a first switching device (201) in series with a second switching device (202) between a node of the signal path and the clamp voltage. The clamping circuitry is configured to be operable in: a first state where the first and second switching devices are both on to electrically connect the signal path to the clamp voltage; and also a second state to electrically disconnect the signal path from the clamp voltage. In the second state one of the first and second switching devices is configured to block conduction when the voltage at said node of the signal path is positive and the other switching device is configured to block conduction when the voltage at said node of the signal path is negative.Type: ApplicationFiled: February 22, 2017Publication date: August 31, 2017Applicant: Cirrus Logic International Semiconductor Ltd.Inventor: Rupesh KHARE
-
Patent number: 8710809Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.Type: GrantFiled: June 28, 2011Date of Patent: April 29, 2014Assignee: STMicroelectronics International N.V.Inventors: Rupesh Khare, Nitin Bansal
-
Publication number: 20130002213Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Rupesh Khare, Nitin Bansal
-
Patent number: 7602162Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.Type: GrantFiled: November 27, 2006Date of Patent: October 13, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventors: Nitin Bansal, Rupesh Khare, Amit Katyal
-
Publication number: 20070194768Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.Type: ApplicationFiled: November 27, 2006Publication date: August 23, 2007Applicant: STMicroelectronics PVT. LTD.Inventors: Nitin Bansal, Rupesh Khare, Amit Katyal