Patents by Inventor Rupin H. Vakharwala

Rupin H. Vakharwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10936490
    Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Edwin Verplanke, Stephen R. Van Doren, Ravishankar Iyer, Eric R. Wehage, Rupin H. Vakharwala, Rajesh M. Sankaran, Jeffrey D. Chamberlain, Julius Mandelblat, Yen-Cheng Liu, Stephen T. Palermo, Tsung-Yuan C. Tai
  • Patent number: 10817447
    Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Rupin H. Vakharwala, Camron B. Rust
  • Publication number: 20200004703
    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
  • Publication number: 20190220413
    Abstract: Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: Rupin H. Vakharwala, Paula Petrica
  • Publication number: 20190102326
    Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.
    Type: Application
    Filed: September 30, 2017
    Publication date: April 4, 2019
    Inventors: Ishwar Agarwal, Rupin H. Vakharwala, Rajesh M. Sankaran, Stephen R. Van Doren
  • Patent number: 10248574
    Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Rupin H. Vakharwala, Eric A. Gouldey, Camron B. Rust, Brett Ireland, Rajesh M. Sankaran
  • Publication number: 20180373633
    Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Inventors: Andrew J. Herdrich, Edwin Verplanke, Stephen R. Van Doren, Ravishankar Iyer, Eric R. Wehage, Rupin H. Vakharwala, Rajesh M. Sankaran, Jeffrey D. Chamberlain, Julius Mandelblat, Yen-Cheng Liu, Stephen T. Palermo, Tsung-Yuan C. Tai
  • Publication number: 20180349288
    Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Inventors: Rupin H. Vakharwala, Eric A. Gouldey, Camron B. Rust, Brett Ireland, Rajesh M. Sankaran
  • Patent number: 10048881
    Abstract: An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, Prashant Sethi, Asit K. Mallick, David Woodhouse, Rupin H. Vakharwala
  • Publication number: 20180137069
    Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Rupin H. Vakharwala, Camron B. Rust
  • Patent number: 9954792
    Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Kevin B. Theobald, Rupin H. Vakharwala, Robert J. Toepfer, Erik G. Hallnor, Robert P. Adler
  • Publication number: 20180011651
    Abstract: An apparatus includes an extended capability register and an input/output (I/O) memory management circuitry. The I/O memory management circuitry is to receive, from an I/O device, an address translation request referencing a guest virtual address associated with a guest virtual address space of a virtual machine. The I/O memory management circuitry may translate the guest virtual address to a guest physical address associated with a guest physical address space of the virtual machine, and, responsive to determining that a value stored by the extended capability register indicates a restrict-translation-request-response (RTRR) mode, transmit, to the I/O device, a translation response having the guest physical address.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 11, 2018
    Inventors: Rajesh M. Sankaran, Prashant Sethi, Asit K. Mallick, David Woodhouse, Rupin H. Vakharwala
  • Publication number: 20160182391
    Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.
    Type: Application
    Filed: December 20, 2014
    Publication date: June 23, 2016
    Inventors: Kevin B. Theobald, Rupin H. Vakharwala, Robert J. Toepfer, Erik G. Hallnor, Robert P. Adler
  • Patent number: 9021156
    Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 28, 2015
    Inventors: Prashanth Nimmala, Robert J. Greiner, Lily P. Looi, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens, Aimee D. Wood, Jeff V. Tran
  • Publication number: 20130054845
    Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Prashanth Nimmala, Robert J. Greiner, Lily P. Looi, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens, Aimee D. Wood, Jeff V. Tran
  • Patent number: 7370160
    Abstract: A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Steven M. Bennett, Andrew V. Anderson, Dion Rodgers, David Koufaty, Richard A. Uhlig, Camron B. Rust, Larry O. Smith, Rupin H. Vakharwala