Abstract: The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid. The present invention also discloses a corresponding system-on-chip and an intelligent device including the system-on-chip.

Abstract: An apparatus includes instruction fetching circuitry to read a set of instructions, including a speculative execution instruction and a speculative condition determination instruction; cache the instructions; and read the speculative execution instruction corresponding to the speculative condition of the speculative condition determination instruction. If an execution result of the speculative condition determination instruction indicates the speculative condition is incorrect, clear the instructions cached in the instruction fetching circuitry. Instruction decoding circuitry decodes instructions. Executing circuitry executes instructions, including executing the speculative condition determination instruction to obtain the execution result.

Abstract: Embodiments of the present disclosure provide an instruction processing apparatus, comprising an instruction decoding circuitry configured to decode a set of instructions; a buffer comprising one or more buffer entries associated with the set of instructions, wherein the one or more buffer entries are configured to store information corresponding to at least one instruction of the set of instructions decoded by the instruction decoding circuitry; and an instruction executing circuitry configured to execute the at least one instruction, wherein a buffer entry storing the information corresponding to the at least one instruction is updated to indicate that the at least one instruction has been executed to enable retiring the set of instructions after the set of instructions have been executed.

Abstract: The present disclosure provides a cutting method of a display module, including: providing a display module to be cut, the display module to be cut including a display panel and a spacing layer on the display panel, and the display panel including a region to be cut, the spacing layer being provided with a first through hole exposing the region to be cut, and the first through hole being provided therein with an encapsulation adhesive; and performing laser cutting on the display module to be cut at a position of the region to be cut so as to remove the region to be cut to form a cutting groove. In the laser cutting, at least part of the encapsulation adhesive is melted and covers a sidewall of the cutting groove.

Abstract: A display panel includes: a back plane; at least one subpixel arranged on the back plane and including a light-emitting material layer; a pixel definition layer provided with first apertures corresponding to subpixels respectively, each subpixel being located within a corresponding first aperture; and a black matrix arranged at a side of the pixel definition layer away from the back plane and provided with second apertures corresponding to the first apertures respectively. A projection of each first aperture onto the back plane is located within a projection of a corresponding second aperture onto the back plane, a center of each second aperture is offset toward a peripheral point of the light-emitting material layer closest to the black matrix relative to a center of the corresponding first aperture, and the light-emitting material layer is in an inclined state relative to the pixel definition layer.

Abstract: Embodiments of the present disclosure provide an instruction processing apparatus, comprising an instruction decoding circuitry configured to decode a set of instructions; a buffer comprising one or more buffer entries associated with the set of instructions, wherein the one or more buffer entries are configured to store information corresponding to at least one instruction of the set of instructions decoded by the instruction decoding circuitry; and an instruction executing circuitry configured to execute the at least one instruction, wherein a buffer entry storing the information corresponding to the at least one instruction is updated to indicate that the at least one instruction has been executed to enable retiring the set of instructions after the set of instructions have been executed.

Abstract: The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid.

Abstract: Embodiments of the present disclosure provide an apparatus, comprising: an instruction fetching circuitry configured to: read a set of instructions, wherein the set of instructions comprises a speculative execution instruction and a speculative condition determination instruction, and the speculative execution instruction is an instruction to be executed according to a speculative condition of the speculative condition determination instruction; cache one or more instructions of the set of instructions in the instruction fetching circuitry; in response to a determination that the speculative condition determination instruction has been read, read the speculative execution instruction corresponding to the speculative condition of the speculative condition determination instruction, and in response to a determination that an execution result of the speculative condition determination instruction indicates that the speculative condition is incorrect, clear the one or more instructions cached in the instruction f