Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.