Abstract: Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

Abstract: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Abstract: Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.

Abstract: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Abstract: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Abstract: Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.

Abstract: Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

Abstract: A power throttling method and system for a memory controller in a computer system comprising a power supply module including a plurality of bulk power supplies (“BPSs”) are described. In one embodiment, each of the at BPSs provides to a power output monitor a status signal indicative of a status thereof. Responsive to receipt of the status signals, the power output monitor determines whether a bulk power supply capacity is below system power requirements. Responsive to a positive determination, the power output monitor drives a throttle control signal to the memory controller to a level indicative of an over-threshold state.

Abstract: Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

Abstract: Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.

Abstract: In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect the multiple cells with the global crossbar network. In an embodiment, the system further includes at least one cell-to-cell connector, to directly connect at least one pair of the multiple cells. In another embodiment, the system further includes one or more local crossbar networks, multiple cell-to-local-crossbar connectors, and local input/output backplanes connected to the one or more local crossbar networks.

Abstract: Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.

Abstract: Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

Abstract: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Abstract: A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

Abstract: A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

Abstract: A system for implementing polygon edging of objects in a graphics display. In a first pass, the system renders the polygon fill with z-buffer comparison and replace enabled, however, for each pixel written to the display frame buffer and z-buffer, an edging plane bit for the pixel is set. A second pass renders the polygon edges with z-buffer comparison and z-buffer replace enabled and uses the edging plane bit as a virgin bit. A third pass re-renders the polygon fill, but only resets the edging plane bit for each pixel. The system may also use a virgin bit available in the z-buffer as the edging plane bit.