Abstract: Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.

Abstract: N-bit precision digital-to-analog converters are provided that facilitate realization of precision linearities (i.e., linearities that substantially exceed N-bit linearity). They include a binary-weighted current source, current switches and bidirectional-trim digital-to-analog converters. The binary-weighted current source generates binary-weighted currents that are each coupled to the output port by a respective one of the current switches in response to a respective bit of the digital input signal. The bidirectional-trim digital-to-analog converters generate respective bidirectional trim currents with respective amplitudes and directions. Each of the bidirectional-trim digital-to-analog converters is coupled to provide its bidirectional trim current to a respective one of the current switches for a linearizing adjustment of that switch's binary-weighted current. Preferably, the bidirectional-trim currents are slaved to the binary-weighted currents.