Patents by Inventor Russell A. Blaine

Russell A. Blaine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10417054
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Patent number: 10310891
    Abstract: Disclosed herein are systems, methods, and computer-readable media directed to scheduling threads in a multi-processing environment that can resolve a priority inversion. Each thread has a scheduling state and a context. A scheduling state can include attributes such as a processing priority, classification (background, fixed priority, real-time), a quantum, scheduler decay, and a list of threads that may be waiting on the thread to make progress. A thread context can include registers, stack, other variables, and one or more mutex flags. A first thread can hold a resource with a mutex, the first thread having a low priority. A second thread having a scheduling state with a high priority can be waiting on the resource and may be blocked behind the mutex held by the first process. A scheduler can execute the context of the lower priority thread using the scheduler state of the second, higher priority thread. More than one thread can be waiting on the resource held by the first thread.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventors: Daniel A. Chimene, Daniel A. Steffen, James M Magee, Russell A. Blaine, Shantonu Sen
  • Publication number: 20190155656
    Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 23, 2019
    Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, James M. Magee
  • Publication number: 20180349175
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
  • Publication number: 20180349186
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Publication number: 20180349177
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Constantin Pistol, Daniel A. Chimene, Jeremy C. Andrus, Russell A. Blaine, Kushal Dalmia
  • Publication number: 20180349261
    Abstract: According to one embodiment, it is determined whether data stored in a compressor pool exceeds a first predetermined threshold, the compressor pool being a fixed-size memory pool maintained in a kernel of an operating system. The compressor pool stores a plurality of compressed memory pages, each memory page storing compressed data pages that can be paged out to or paged in from a persistent storage device. The compressed memory pages are associated with a plurality of processes. A memory consumption reduction action is performed to reduce memory usage, including terminating at least one of the processes to reclaim a memory space occupied by the process, in response to determining that the data stored in the compressor pool exceeds the first predetermined threshold.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 6, 2018
    Inventors: LIONEL D. DESAI, RUSSELL A. BLAINE, BENJAMIN C. TRUMBULL
  • Publication number: 20180349181
    Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.
    Type: Application
    Filed: December 8, 2017
    Publication date: December 6, 2018
    Inventors: Daniel A. Steffen, Jainam A. Shah, James M. Magee, Jeremy C. Andrus, Russell A. Blaine
  • Publication number: 20180349176
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Publication number: 20180349182
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Patent number: 10140157
    Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 27, 2018
    Assignee: Apple Inc.
    Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, James M. Magee
  • Publication number: 20180088985
    Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.
    Type: Application
    Filed: October 17, 2017
    Publication date: March 29, 2018
    Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, John Dorsey, Bryan Hinch, Cyril De La Cropte De Chanterac, Oliver Cozette
  • Patent number: 9830187
    Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: November 28, 2017
    Assignee: Apple Inc.
    Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, John Dorsey, Bryan Hinch, Cyril De La Cropte De Chanterac, Olivier Cozelle
  • Patent number: 9772959
    Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 26, 2017
    Assignee: Apple Inc.
    Inventors: Russell A. Blaine, Kushal Dalmia, Joseph Sokol, Jr., Andrew W. Vogan, Matthew J. Byom
  • Publication number: 20170269967
    Abstract: In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.
    Type: Application
    Filed: February 27, 2017
    Publication date: September 21, 2017
    Inventors: Daniel A. Steffen, Matthew W. Wright, Russell A. Blaine, Daniel A. Chimene, Kevin J. Van Vechten, Thomas B. Duffy
  • Patent number: 9727577
    Abstract: A cloud storage system identifies and creates metadata associated with a stored file. On receiving a request to access the file with an application, the cloud storage system generates a metadata category associated only with the application, and creates metadata associated with the generated metadata category and corresponding to the file. On receiving a request to access file metadata, the cloud storage system identifies an application associated with the metadata access request, identifies a set of metadata categories associated with the identified application, filters metadata associated with the file based on the identified set of metadata categories, and provides the filtered metadata to the application.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 8, 2017
    Assignee: GOOGLE INC.
    Inventors: Alain Vongsouvanh, Russell Blaine Jorgensen, Robert Eugene Wyrick, Justin Lee Hicks, Stephen Nowland Clark
  • Patent number: 9690685
    Abstract: A method and apparatus of a device for performance management by terminating application programs that consume an excessive amount of system resources is described. The device receives a resource consumption threshold and a detection period. The device further monitors a resource usage of an application program. The device determines whether the resource usage of the application program exceeds the resource consumption threshold for the detection period. The device further terminates the application program when the resource usage exceeds the resource consumption threshold for the detection period.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 27, 2017
    Assignee: Apple Inc.
    Inventors: Amit K. Vyas, Albert S. Liu, Anand Ramadurai, Drew A. Schmitt, Russell A. Blaine, Karen Crippes
  • Patent number: 9665398
    Abstract: A method and an apparatus for activity based execution scheduling are described. Activities may be tracked among a plurality of threads belonging to a plurality of processes running in one or more processors. Each thread may be associated with one of the activities. Each activity may be associated with one or more of the threads in one or more of the processes for a data processing task. The activities may be ordered by a priority order. A group of the threads may be identified to be associated with a particular one of the activities with highest priority based on the priority order. A thread may be selected from the identified threads for next scheduled execution in the processors.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 30, 2017
    Assignee: Apple Inc.
    Inventors: James Michael Magee, Russell A. Blaine, Daniel Allen Chimene, Vishal Patel, Shantonu Sen
  • Patent number: 9582326
    Abstract: In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 28, 2017
    Assignee: Apple Inc.
    Inventors: Daniel A. Steffen, Matthew W. Wright, Russell A. Blaine, Jr., Daniel A. Chimene, Kevin J. Van Vechten, Thomas B. Duffy
  • Publication number: 20160357600
    Abstract: Disclosed herein are systems, methods, and computer-readable media directed to scheduling threads in a multi-processing environment that can resolve a priority inversion. Each thread has a scheduling state and a context. A scheduling state can include attributes such as a processing priority, classification (background, fixed priority, real-time), a quantum, scheduler decay, and a list of threads that may be waiting on the thread to make progress. A thread context can include registers, stack, other variables, and one or more mutex flags. A first thread can hold a resource with a mutex, the first thread having a low priority. A second thread having a scheduling state with a high priority can be waiting on the resource and may be blocked behind the mutex held by the first process. A scheduler can execute the context of the lower priority thread using the scheduler state of the second, higher priority thread. More than one thread can be waiting on the resource held by the first thread.
    Type: Application
    Filed: September 30, 2015
    Publication date: December 8, 2016
    Inventors: Daniel A. CHIMENE, Daniel A. STEFFEN, James M. MAGEE, Russell A. BLAINE, Shantonu SEN