Abstract: A data processor is provided with status logic for monitoring the instruction processing activity therein, and for providing a pulse width encoded status output signal having either a first duration if the next instruction is to be executed in a normal sequence, or a second duration if an exception condition has occurred which will delay or prevent the execution of the next instruction. In the preferred form, the status logic can detect various types of exception conditions in the CPU and will assert the status signal for respective durations for each such type. In a data processor having an internal instruction pipeline, the status logic may also monitor changes in the flow of instructions, and provide a "refill" signal to indicate that the prefetched instructions in the pipeline have be discarded.