Patents by Inventor Russell Carlton McMULLAN
Russell Carlton McMULLAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10461075Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: GrantFiled: September 24, 2015Date of Patent: October 29, 2019Assignee: Texas Instruments IncorporatedInventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
-
Patent number: 9985018Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: GrantFiled: September 24, 2015Date of Patent: May 29, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
-
Patent number: 9966373Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.Type: GrantFiled: January 19, 2017Date of Patent: May 8, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Russell Carlton McMullan, Kamel Benaissa
-
Publication number: 20170133366Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Inventors: Russell Carlton McMullan, Kamel Benaissa
-
Patent number: 9589983Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.Type: GrantFiled: June 3, 2016Date of Patent: March 7, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Russell Carlton McMullan
-
Patent number: 9583609Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.Type: GrantFiled: March 25, 2013Date of Patent: February 28, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Russell Carlton McMullan, Kamel Benaissa
-
Publication number: 20160284731Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventor: Russell Carlton McMullan
-
Patent number: 9385140Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.Type: GrantFiled: February 4, 2015Date of Patent: July 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Russell Carlton McMullan
-
Publication number: 20160071839Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: ApplicationFiled: September 24, 2015Publication date: March 10, 2016Inventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
-
Publication number: 20160071838Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: ApplicationFiled: September 24, 2015Publication date: March 10, 2016Inventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
-
Patent number: 9184226Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: GrantFiled: August 15, 2012Date of Patent: November 10, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
-
Patent number: 9093315Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.Type: GrantFiled: December 8, 2013Date of Patent: July 28, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shaofeng Yu, Russell Carlton McMullan, Wah Kit Loh
-
Patent number: 8962419Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.Type: GrantFiled: September 26, 2014Date of Patent: February 24, 2015Assignee: Texas Instruments IncorporatedInventors: Russell Carlton McMullan, Dong Joo Bae
-
Publication number: 20150011061Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.Type: ApplicationFiled: September 26, 2014Publication date: January 8, 2015Inventors: Russell Carlton McMULLAN, Dong Joo BAE
-
Publication number: 20140346609Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.Type: ApplicationFiled: December 8, 2013Publication date: November 27, 2014Applicant: Texas Instruments IncorporatedInventors: Shaofeng Yu, Russell Carlton McMullan, Wah Kit Loh
-
Patent number: 8871587Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.Type: GrantFiled: July 21, 2009Date of Patent: October 28, 2014Assignee: Texas Instruments IncorporatedInventors: Russell Carlton McMullan, Dong Joo Bae
-
Publication number: 20140284725Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.Type: ApplicationFiled: March 25, 2013Publication date: September 25, 2014Applicant: Texas Instruments IncorporatedInventors: Russell Carlton McMullan, Kamel Benaissa
-
Patent number: 8603875Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.Type: GrantFiled: October 28, 2011Date of Patent: December 10, 2013Assignee: Texas Instruments IncorporatedInventors: Shaofeng Yu, Russell Carlton McMullan, Wah Kit Loh
-
Publication number: 20130207221Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.Type: ApplicationFiled: August 15, 2012Publication date: August 15, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Russell Carlton McMullan, Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith Edmund Kunz
-
Publication number: 20120104510Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.Type: ApplicationFiled: October 28, 2011Publication date: May 3, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Shaofeng Yu, Russell Carlton McMullan, Wah Kit Loh