Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

Abstract: Selectively transmitting cache misses within multiple-node shared-memory systems employing coherence protocols is disclosed. A cache-coherent system includes a number of nodes employing a coherence protocol to maintain cache coherency, as well as memory that is divided into a number of memory units. There is a cache within each node to temporarily store contents of the memory units. Each node further has logic to determine whether a cache miss relating to a memory unit should be transmitted to one or more of the other nodes lesser in number than the total number of nodes within the system. This determination is based on whether, to ultimately reach the owning node for the memory unit, such transmission is likely to reduce total communication traffic among the total number of nodes and unlikely to increase latency as compared to broadcasting the cache miss to all the nodes within the system.

Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.