Abstract: A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers.

Abstract: Apparatus and system for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.

Abstract: Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.

Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.

Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.

Abstract: Methods and devices that may be utilized in systems to dynamically update a security version parameter used to encrypt secure data are provided. The version may be maintained in persistent storage located on a device implementing the encryption, such as a system on a chip (SOC). The persistent storage does not require battery backing and, thus, the cost and complexity associated with conventional systems utilizing battery backed storage may be reduced.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

Abstract: According to embodiments of the invention, separate spatial indexes may be created which correspond to dynamic objects in a three dimensional scene and static objects in the three dimensional scene. By creating separate spatial indexes for static and dynamic objects, only the dynamic spatial index may need to be rebuilt in response to movement or changes in shape of objects in the three dimensional scene. Furthermore, the static and dynamic spatial indexes may be stored in separate portions of an image processing system's memory cache. By storing the static spatial index and the dynamic spatial index in separate portions of the memory cache, the dynamic portion of the memory cache may be updated without affecting the static portion of the spatial index in the memory cache.

Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

Abstract: A method and apparatus are provided for maintaining a N-way associative directory utilizing a content addressable memory (CAM). A congruence class from the N-way associative directory including a directory entry identified for a data operation is read into the CAM for the data operation. The directory entry for the data operation in the CAM is locked while the data operation is pending. Other entries in the congruence class are available. When the data operation is completed, checking for a state change is performed. Responsive to an identified state change, the directory entry for the data operation in the CAM is updated or marked as changed. The congruence class including the updated directory entry is marked as dirty. In accordance with features of the invention, the changed congruence class directory entries in the CAM are accumulated and scheduled to be written back to the N-way associative directory.

Abstract: A multiprocessor in which processing units have local private caches and records are stored on at least a first global storage control unit. An interconnection system provides node to node data and synchronization communications between processing units and the first global storage control unit. The global storage control unit includes a coherency controller for tracking each instance of records owned by the global storage control unit currently resident on the processing units. Each processing unit executes a cache management process for freeing intervals of the local cache for the processing unit. Upon identification of an interval, the processing unit sends empty notification to the global storage control unit owning the record an instance of which was resident in the interval. Thereafter the interval is marked as invalid in a cache directory for the processing unit and indicia for the instance is deleted from a coherency directory for the global storage control unit.

Abstract: A hardware data string operation controller is provided which (1) performs variable length main store string operation; (2) executes at least a subset of both left to right and right to left instructions, having variable length multibyte operands; and (3) performs multicycle storage to storage operations on variable length multibyte operand data, all under the control of a single control word. The controller comprises (a) means for dynamically determining (and if necessary, adjusting) the maximum number of operand related data string bytes that can be processed (by the controller) during each machine cycle (referred to as"data mode" calculation/alteration); (b) means for performing partial machine "holdoffs" (i.e.