Abstract: A versatile and efficient technique for classifying packets in an intermediate node. According to the technique, criteria and rules associated with the packet are applied to one or more classification stages containing content-addressable memories (CAMs). Each stage examines specific criteria associated with the packet, e.g., a packet field, and generates a rule and additional criteria. The additional rule and criteria are provided to the next classification stage. This process continues until a final rule is provided to a final classification stage. At the final classification stage, the final rule is used to generate an identifier, e.g., queue identifier (ID), associated with the classified packet.

Abstract: A versatile and efficient technique for classifying packets in an intermediate node. According to the technique, criteria and rules associated with the packet are applied to one or more classification stages containing content-addressable memories (CAMs). Each stage examines specific criteria associated with the packet, e.g., a packet field, and generates a rule and additional criteria. The additional rule and criteria are provided to the next classification stage. This process continues until a final rule is provided to a final classification stage. At the final classification stage, the final rule is used to generate an identifier, e.g., queue identifier (ID), associated with the classified packet.

Abstract: An ATM communications network includes a system processor having a device driver and a memory coupled to an adapter at an interface. Frames stored in the memory are transmitted to the network using a transmit ready queue residing in the adapter and defined by transmit control registers. The frames are linked together by descriptors and pointers to received ready lists maintained by the device driver. A transmit frame complete list is established in the system memory using the transmit control registers. An interrupt is generated by the adapter indicating when frame transmission is complete. Simultaneously, cells are received from the network and stored in system memory according to a free buffer list established by the device driver. A pointer is maintained by the device driver to the last entry of the receive free buffer list. The adapter maintains a pointer to the next buffer to be used from the receive free buffer list.

Abstract: A mechanism prioritizes cross interrogate requests between multiple requestors in a multi-processor system where the delay due to cable length interconnecting requestors results in requests not being received within one machine cycle. Local and remote cross interrogate (XI) requests are latched up in storage control element (SCE) temporary registers before being prioritized. The local request is staged in a local delay register. The local request is selected from the local delay register by synchronization control logic, instead of the temporary register, when the remote request is issued one cycle earlier than the local request, or when both local and remote requests are issued at the same time, but the remote requests is from a master SCE. The staging of the local requests can be extended to multiple cycles, corresponding to the length of the cables between SCEs.