Patents by Inventor Russell Fagg
Russell Fagg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9438171Abstract: A circuit having a first transistor being a common gate connected transistor and a second transistor, the second transistor being M times the size of the first transistor, the first and second transistors having commonly connected gates and commonly connected drains, wherein an apparatus is provided to regulate the source voltage of the second transistor to track the source voltage of the first transistor, wherein the current gain of the circuit is M+1.Type: GrantFiled: January 23, 2015Date of Patent: September 6, 2016Assignee: SNAPTRACK, INC.Inventor: Russell Fagg
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Patent number: 9257941Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.Type: GrantFiled: November 26, 2014Date of Patent: February 9, 2016Assignee: SNAPTRACK, INC.Inventor: Russell Fagg
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Publication number: 20150214898Abstract: A circuit having a first transistor being a common gate connected transistor and a second transistor, the second transistor being M times the size of the first transistor, the first and second transistors having commonly connected gates and commonly connected drains, wherein an apparatus is provided to regulate the source voltage of the second transistor to track the source voltage of the first transistor, wherein the current gain of the circuit is M+1.Type: ApplicationFiled: January 23, 2015Publication date: July 30, 2015Inventor: Russell Fagg
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Publication number: 20150145596Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.Type: ApplicationFiled: November 26, 2014Publication date: May 28, 2015Inventor: Russell Fagg
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Patent number: 8902002Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.Type: GrantFiled: May 30, 2012Date of Patent: December 2, 2014Assignee: Nujira LimitedInventor: Russell Fagg
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Patent number: 8854139Abstract: There is described an amplification stage comprising: a current mirror circuit comprising a reference transistor arranged to receive a current associated with an input signal and an output transistor providing a current source for an output signal line; a current sink to the output signal line, under the control of the input signal; circuitry arranged to maintain equality between the drain/collector voltages on the transistors of the current mirror circuit.Type: GrantFiled: May 30, 2012Date of Patent: October 7, 2014Assignee: Nujira LimitedInventor: Russell Fagg
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Publication number: 20130321081Abstract: There is described an amplification stage comprising: a current mirror circuit comprising a reference transistor arranged to receive a current associated with an input signal and an output transistor providing a current source for an output signal line; a current sink to the output signal line, under the control of the input signal; circuitry arranged to maintain equality between the drain/collector voltages on the transistors of the current mirror circuit.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: NUJIRA LIMITEDInventor: Russell Fagg
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Publication number: 20130321085Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: NUJIRA LIMITEDInventor: Russell Fagg
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Patent number: 8130020Abstract: A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.Type: GrantFiled: May 13, 2008Date of Patent: March 6, 2012Assignee: Qualcomm IncorporatedInventor: Russell Fagg
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Publication number: 20100225419Abstract: A passive switched-capacitor (PSC) filter includes (i) an array of capacitors that can store and share electrical charge and (ii) an array of switches that can couple the capacitors to a summing node. Each switch couples an associated capacitor to the summing node when enabled. Each capacitor stores a voltage value from the summing node when selected for charging and shares electrical charge with other capacitors via the summing node when selected for charge sharing. The PSC filter may include multiple sections for multiple filter taps. Each section includes one or more capacitors of equal size determined based on a corresponding filter coefficient. The capacitors in each section may be sequentially selected for charging with an input or output signal, one capacitor in each clock cycle. In each clock cycle, one capacitor in each section may be selected for charge sharing to generate the output signal.Type: ApplicationFiled: March 9, 2009Publication date: September 9, 2010Applicant: QUALCOMM IncorporatedInventors: Chengzhi Pan, Joseph Burke, Russell Fagg
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Patent number: 7656230Abstract: A device for providing low noise transconductance amplification is presented. The device includes a PMOS transconductance section configured to receive a differential RF input signal, a PMOS cascode section coupled to the PMOS transconductance section, an NMOS transconductance section configured to receive the RF differential input signal, and an NMOS cascode section coupled to the NMOS transconductance section, where the PMOS and NMOS cascode sections provide a differential quadrature output signal and a differential in-phase output signal. A method for amplifying an RF signal is also presented. The method includes receiving a differential RF input signal, converting the differential RF input signal into current signals, buffering the current signals to provide a differential quadrature output signal and a differential in-phase output signal.Type: GrantFiled: March 21, 2008Date of Patent: February 2, 2010Assignee: QUALCOMM, IncorporatedInventor: Russell Fagg
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Publication number: 20090284285Abstract: A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.Type: ApplicationFiled: May 13, 2008Publication date: November 19, 2009Applicant: QUALCOMM INCORPORATEDInventor: Russell Fagg
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Publication number: 20090237161Abstract: A device for providing low noise transconductance amplification is presented. The device includes a PMOS transconductance section configured to receive a differential RF input signal, a PMOS cascode section coupled to the PMOS transconductance section, an NMOS transconductance section configured to receive the RF differential input signal, and an NMOS cascode section coupled to the NMOS transconductance section, where the PMOS and NMOS cascode sections provide a differential quadrature output signal and a differential in-phase output signal. A method for amplifying an RF signal is also presented. The method includes receiving a differential RF input signal, converting the differential RF input signal into current signals, buffering the current signals to provide a differential quadrature output signal and a differential in-phase output signal.Type: ApplicationFiled: March 21, 2008Publication date: September 24, 2009Applicant: QUALCOMM INCORPORATEDInventor: Russell Fagg
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Patent number: 7501900Abstract: A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.Type: GrantFiled: May 31, 2006Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Christopher Hull, Russell Fagg, Dandan Li
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Publication number: 20070279135Abstract: A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Inventors: Christopher Hull, Russell Fagg, Dandan Li