Patents by Inventor Russell Fields

Russell Fields has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GROUP III-V SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION OF SAME INCLUDING IN-SITU SURFACE PASSIVATION
    Publication number: 20240105450
    Abstract: A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.
    Type: Application
    Filed: December 29, 2022
    Publication date: March 28, 2024
    Inventors: Yoganand Saripalli, Russell Fields, Brian Goodlin, Qhalid Fareed
  • DUAL DEPTH TRENCH TERMINATION METHOD FOR IMPROVING CU-BASED INTERCONNECT INTEGRITY
    Publication number: 20090121358
    Abstract: A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge ? of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150, 160) to form the interconnect line.
    Type: Application
    Filed: May 12, 2008
    Publication date: May 14, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajesh Tiwari, Russell Fields, Scott A. Boddicker, Andrew Tae Kim
  • Dual depth trench termination method for improving Cu-based interconnect integrity
    Patent number: 7387960
    Abstract: A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge ? of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150), (160) to form the interconnect line.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: June 17, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Rajesh Tiwari, Russell Fields, Scott A. Boddicker, Andrew Tae Kim
  • Dual depth trench termination method for improving Cu-based interconnect integrity
    Publication number: 20050059189
    Abstract: A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge ? of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150), (160) to form the interconnect line.
    Type: Application
    Filed: September 16, 2003
    Publication date: March 17, 2005
    Inventors: Rajesh Tiwari, Russell Fields, Scott Boddicker, Andrew Kim