Abstract: As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers that have been developed and honed over many years. The reliability and robustness of the legacy system and its emulated replacement are of utmost importance. Since the emulation system software is new and complex it may have undiscovered errors in coding which if encountered may result in an abort of the emulation program itself. This software emulation program abort is akin to a logic failure or bug in the legacy system hardware. Utilizing a signal handler in analysis and recovery from coding errors, while not taking greater risk of data corruption, increases the stability and robustness of the emulated computer system and is akin to hardware error correction in the legacy system hardware design.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers. High performance is typically a key requirement for a system even when built using emulation software. In a hardware design many special cases and conditions which may cause exceptions are detected by logic operating in parallel with the instruction execution. In software these checks can cost extra cycles of processor time during emulation of each instruction and be a significant detriment to performance. Avoiding some of these checks by relying upon the underlying hardware checks of the host system and then using a signal handler and special software to recover from these signals is a way to improve the performance and simplify the coding of the software emulation system.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate the proprietary hardware systems of powerful older computers on platforms built using commodity processors. The systems being emulated are often large mainframe computers with large numbers of disks, communications systems and other attached hardware. Because of the size and expense, and also because databases involved must reside in only one location, it is difficult to replicate these systems for testing, development, debug or for providing alternative options to customers. A method for providing a single emulated computer system which provides for multiple views or options in control of the emulator is disclosed in which the options are dependent and selected based on job or user basis. The mechanism continues to provide for high performance and a single copy of the operating system with multiple processes, jobs and threads being emulated under user controlled parameters.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary legacy hardware systems of powerful older computers. High performance is often a key requirement for a system even when built using emulation software. Within the hardware of the legacy system the memory management software and paging hardware is often complex, and takes considerable code in the software emulator to emulate. If the segments of data referenced by a program running under the software emulator can be placed in contiguous linear memory, the memory management software and the work of the software emulator can be reduced to improve performance and reduce complexity of the emulated system.

Abstract: A process for sorting large files or structures is disclosed where improved performance is achieved by reducing the work involved and the time required to do record key comparisons. The reduction is achieved by transposing and saving the key data from each record into a representative form that can be more quickly compared each time the key comparison is required. In addition the process uses pointers to avoid the processing time to exchange records larger than one word in memory. The representation of the key data is optimized and aligned for comparison by word based computer instructions which are typically faster than byte based instructions. The process is optimized for word sizes and instructions which handle words larger than four bytes and in particular for machines and instructions with 64-bit or larger word sizes such as the Intel Itanium series processors.

Abstract: In order to avoid hardware pipeline breaks and also to enhance performance when emulating a target system in a host system employing a central processing unit including a plurality of execution units, three major pieces of processing that are required for handling every emulated instruction are overlapped. This overlap includes: 1) the instruction fetch of the emulated instruction by the emulation software, 2) the branching of the emulation code based upon the opcode of the emulated instruction to be executed and 3) the actual execution processing for each emulated instruction. The branching of the emulation code, depending upon the opcode of each instruction, utilizes special instructions configured to minimize pipeline breaks on the host system hardware and thus to minimize the effective minimum host system processing time for the simplest emulated instructions.

Abstract: This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.

Abstract: During the emulation of one computer operating system by a physical computer running another operating system, the occurrence of disruptive external events is detected and accounted for. A predetermined estimate of the work which should be necessary to process each emulated “instruction” is entered into a lookup table. As the emulation program runs, the processing of each instruction includes the addition of work units to a running total of work units required to process a given batch of emulated instructions. A real time measure is also kept for the batch and is ordinarily used to update an accumulated total time measure for time accounting purposes except when external events occur which delay processing for some real, but unknown, amount of time. In this case, the real time measure is an inaccurate measure of work done, and the estimated work units is used to update the accumulated total time measure.

Abstract: A methodology for improving the timing of specific critical paths in a Field Programmable Gate Array (FPGA) implementation of a logic circuit without significantly affecting the timing of other logic paths. The method utilizes logic replication and specific guidelines for placement of the logic gates involved in a critical path to optimize the timing of that critical path. The logic gates involved in a critical path are either replicated and placed, or simply moved, in order to implement the desired logic with nearly the shortest total distance for routing of signals involved in the critical path. The optimization is carried out with relatively little impact on the timing of other paths and is applicable to FPGAs in which the signal delay between any source and gate is relatively independent of the fanout of the source signal to any other loads.