Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: Encoding of a dual mode digital signal for transfer using a dual mode super source follower circuit to drive the signal across a pulse transformer is presented. The dual mode signal includes data in one mode and power/control in the other mode. In the power/control mode the magnitude of the signal pulses are greater than the magnitude of the data pulses. Thus, the current sinking deficiencies of the super source follower may introduce waveform irregularities when transitioning from the high of the power pulse to the high of the data pulse. An encoding method described herein uses a return to zero scheme to avoid such waveform irregularities during power to data transitions.

Abstract: Active rectification with load impedance switching for communication across a pulse transformer is presented. Load impedance switching is used for communicating data from the secondary side of the transformer to the primary side during data frames. During power frames, the load impedance is switched to a capacitor for the storage of charge from received power pulses, which may then be converted into a power source. The active rectifier circuit is configurable to accommodate different power requirements and transformer characteristics, and may be implemented with half-wave or full-wave configurations. In active mode, switches are enabled to short out diodes such that diode voltage losses are overcome in the recovered power supply voltage.

Abstract: Encoding of a dual mode digital signal for transfer using a dual mode super source follower circuit to drive the signal across a pulse transformer is presented. The dual mode signal comprises data in one mode and power/control in the other mode. In the power/control mode the magnitude of the signal pulses are greater than the magnitude of the data pulses. Thus, the current sinking deficiencies of the super source follower may introduce waveform irregularities when transitioning from the high of the power pulse to the high of the data pulse. An encoding method described herein uses a return to zero scheme to avoid such waveform irregularities during power to data transitions.

Abstract: A feedback method and apparatus for cancellation of magnetizing inductance current are presented. A voltage driver applies a voltage signal to a primary of a transformer. Feedback apparatus detect changes in the voltage driver output current that are attributable to magnetizing inductance current. Changes in output current are used to obtain a current error, which is integrated to control a current ramp generator. The output of the current ramp generator is applied to the transformer primary as a compensating current for canceling the magnetizing inductance current.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: Encoding of a dual mode digital signal for transfer using a dual mode super source follower circuit to drive the signal across a pulse transformer is presented. The dual mode signal comprises data in one mode and power/control in the other mode. In the power/control mode the magnitude of the signal pulses are greater than the magnitude of the data pulses. Thus, the current sinking deficiencies of the super source follower may introduce waveform irregularities when transitioning from the high of the power pulse to the high of the data pulse. An encoding method described herein uses a return to zero scheme to avoid such waveform irregularities during power to data transitions.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses is used initially to obtain the parameters for and to set up a phase locked loop. For example, an edge-triggered one-shot circuit can be used to generate a reference clock from the preamble until lock is detected. Once the phase lock loop locks onto the clock, normal communication between the primary and secondary commences. The phase lock loop, which is in the secondary, is kept in phase during normal communication using valid Manchester edges from the transmit signal.

Abstract: A high speed ramp generator is presented. The high speed ramp generator is advantageous over the prior art because it provides a ramp response without the delay incident with a simple integrator approach. A closed loop system generates a continuous ramp and, in an open loop manner, subtracts a mirror of the current ramp from itself. A switch is provided which when open, triggers an immediate current ramp output that is not dependent on the amplifier or any other component of prior art feedback circuits. Two such ramp generators may be used in tandem to provide alternating portions of a precision ramp signal, such as may be used to cancel the magnetization current induced in the primary of an isolation transformer.

Abstract: A feedback method and apparatus for cancellation of magnetizing inductance current are presented. A voltage driver applies a voltage signal to a primary of a transformer. Feedback apparatus detect changes in the voltage driver output current that are attributable to magnetizing inductance current. Changes in output current are used to obtain a current error, which is integrated to control a current ramp generator. The output of the current ramp generator is applied to the transformer primary as a compensating current for canceling the magnetizing inductance current.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: Encoding of a dual mode digital signal for transfer using a dual mode super source follower circuit to drive the signal across a pulse transformer is presented. The dual mode signal comprises data in one mode and power/control in the other mode. In the power/control mode the magnitude of the signal pulses are greater than the magnitude of the data pulses. Thus, the current sinking deficiencies of the super source follower may introduce waveform irregularities when transitioning from the high of the power pulse to the high of the data pulse. An encoding method described herein uses a return to zero scheme to avoid such waveform irregularities during power to data transitions.

Abstract: Active rectification with load impedance switching for communication across a pulse transformer is presented. Load impedance switching is used for communicating data from the secondary side of the transformer to the primary side during data frames. During power frames, the load impedance is switched to a capacitor for the storage of charge from received power pulses, which may then be converted into a power source. The active rectifier circuit is configurable to accommodate different power requirements and transformer characteristics, and may be implemented with half-wave or full-wave configurations. In active mode, switches are enabled to short out diodes such that diode voltage losses are overcome in the recovered power supply voltage.

Abstract: A high speed ramp generator is presented. The high speed ramp generator is advantageous over the prior art because it provides a ramp response without the delay incident with a simple integrator approach. A closed loop system generates a continuous ramp and, in an open loop manner, subtracts a mirror of the current ramp from itself. A switch is provided which when open, triggers an immediate current ramp output that is not dependent on the amplifier or any other component of prior art feedback circuits. Two such ramp generators may be used in tandem to provide alternating portions of a precision ramp signal, such as may be used to cancel the magnetization current induced in the primary of an isolation transformer.

Abstract: A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses is used initially to obtain the parameters for and to set up a phase locked loop. For example, an edge-triggered one-shot circuit can be used to generate a reference clock from the preamble until lock is detected. Once the phase lock loop locks onto the clock, normal communication between the primary and secondary commences. The phase lock loop, which is in the secondary, is kept in phase during normal communication using valid Manchester edges from the transmit signal.

Abstract: Simultaneous bi-directional communication of digital signals across an isolation barrier, such as a pulse transformer, is presented. On the pimary side of the barrier, a voltage driver drives a digital transmit data stream, that is encoded to be DC balanced in both current and voltage domains, across the barrier. On the secondary side, an impedance switching circuit modulates the load impedance of the voltage driver in accordance with a digital receive data stream. The modulation of the load impedance is detected on the primary side by sampling the sourced current of the voltage driver to extract the digital receive data. The voltage driver may be sampled at predictable points in time when the current it is sourcing is primarily dependent upon the load impedance of the secondary side. Alternatively, the magnetizing inductance current of the isolation barrier can be subtracted from the current sourced due to the known transmit data.

Abstract: Simultaneous bi-directional communication of digital signals across an isolation barrier, such as a pulse transformer, is presented. On the pimary side of the barrier, a voltage driver drives a digital transmit data stream, that is encoded to be DC balanced in both current and voltage domains, across the barrier. On the secondary side, an impedance switching circuit modulates the load impedance of the voltage driver in accordance with a digital receive data stream. The modulation of the load impedance is detected on the primary side by sampling the sourced current of the voltage driver to extract the digital receive data. The voltage driver may be sampled at predictable points in time when the current it is sourcing is primarily dependent upon the load impedance of the secondary side. Alternatively, the magnetizing inductance current of the isolation barrier can be subtracted from the current sourced due to the known transmit data.

Abstract: The present disclosure encompasses the use of a current mirror to control the trip point for a power-on-reset circuit. The current mirror is designed to turn on at a multiple of a transistor threshold voltage V.sub.t. The power-on-reset circuit asserts a power-on signal in response to mirror current provided by the current mirror when the supply voltage ramps up above the V.sub.t multiple. Since the transistor threshold voltage may be tightly controlled during the fabrication process, the trip point for the power-on-reset circuit may be precisely and accurately adjusted to match the minimum operating supply voltage level specified for an integrated circuit device such as a microprocessor. Also, a feedback path may be provided in the power-on-reset circuit to turn off the current mirror once the power-on signal is asserted so that there is no current draw in the power-on-circuit for static conditions.

Abstract: The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.