Abstract: Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

Abstract: Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

Abstract: Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

Abstract: Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

Abstract: A communications system, comprising a first device including a first scan table and a second device including a second scan table. The first device is configured to select the first scan table and transmit scan table identification. The second device is configured to receive the scan table identification from the first device and select the second scan table based on the received scan table identification.

Abstract: One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.

Abstract: A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.

Abstract: A communications system comprising a first stage including a first scan table and a second stage including a second scan table. The first stage is configured to select a first channel identification from the first scan table and provide data from a channel identified by the first channel identification. The second stage is configured to receive the data and select a second channel identification from the second scan table to provide the received data at essentially a data rate of the channel on a synchronous network.

Abstract: One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.

Abstract: A device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format, and a serial/parallel converter providing n?2 successive data bits of the serial bit stream as n-bit data words in the parallel format.

Abstract: A network address filter that includes a random access memory configured to store network address data, a processor, and a comparator. The processor is configured to execute a hash function on input data to obtain a random access memory address that is applied to the random access memory to obtain network address data from the random access memory address. The comparator is configured to compare the input data to the network address data and indicate a match between the input data and the network address data.

Abstract: A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.

Abstract: A communications system comprising a first stage including a first scan table and a second stage including a second scan table. The first stage is configured to select a first channel identification from the first scan table and provide data from a channel identified by the first channel identification. The second stage is configured to receive the data and select a second channel identification from the second scan table to provide the received data at essentially a data rate of the channel on a synchronous network.

Abstract: A communications system, comprising a first device including a first scan table and a second device including a second scan table. The first device is configured to select the first scan table and transmit scan table identification. The second device is configured to receive the scan table identification from the first device and select the second scan table based on the received scan table identification.

Abstract: The units (CTR0, CTR1) are controlled by mutually independent clock pulses (SCLK, RXCK). In order to prevent the loss of microsynchronization when information is transferred from one clock system to the other and as a result of different error situations as regards the information received by the units, the information received is temporarily stored before being passed on for processing or the result information is temporarily stored before being transmitted. If reception is error free, the units are cross-synchronized. In the absence of a synchronization signal in one partner unit owing to faulty reception, this unit rejects the information received despite the fact that it is error free.

Abstract: For implementing the method for reading error statistics data, a hardware configuration has processing units (CTR0, CTR1) that operated in microsynchronous parallel operation for the processing of ATM information. The processing units are connected at the ATM end to a switching matrix (SN0, SN1) and via a bus interface (B-I) to a central processor. The central processor is used for evaluating error statistics arising in the processing units and for monitoring the synchronous operation by comparing the processing results. The error statistics data is packed into ATM transmitter cells and looped back via the switching matrix in each case to both processing units and then supplied to the central processor via the bus interface. This prevents the erroneous indication of the loss of microsynchronism when error statistics for the two processing units differ.