Abstract: A system detects a powerdown event, such as a power loss event, and performs a flush of volatile memory to persistent memory during a powerdown sequence. The system includes an energy backup device to power the system during the powerdown sequence. The system is configurable with optional settings that configure the powerdown sequence specific to a type of the energy backup device.

Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.

Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.

Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Abstract: Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: A PCI repeater coupled between a primary bus and a secondary bus transparently decodes upstream transactions by halting operations on the secondary bus while the transaction is decoded on the primary bus. A clock disable signal is internally generated to temporarily disable the bus clock on the secondary bus. Transactions initiated on the secondary bus are first sent upstream regardless of whether or not the target is upstream. If the transaction is not positively claimed by a target on the upstream bus, the PCI repeater subtractively claims the transaction. Special upstream decoding logic in the PCI repeater is avoided by sending the transaction upstream and using the inherent decoding logic of PCI devices.

Abstract: The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided. The RAM is only programmed once, with modifications to the RAM-provided write protect status and memory location values being made based on write protect and relocation status information contained in a separate register.