Abstract: A method and device for driving signals over a capacitive bus is provided. The device comprises at least one input line selectively activatable for receiving an input signal having a first voltage level. A drive capacitor is positioned in series with and between each of the input lines and the capacitive bus to be driven. The drive capacitor and a capacitance of the capacitive bus forms a capacitive divider network which reduces the input signal to render an intermediate signal having a second voltage level less than the first voltage level. Each of the drive capacitors is also provided with a pre-charge input for receiving a pre-charge voltage signal when its corresponding input line is not selectively activated. At least one amplifier is provided for amplifying the intermediate signal to produce an output signal on an output line having a third voltage level which is approximately the same as the first voltage level.

Abstract: A column of an integrated memory circuit includes two bit lines each with a right half and a left half and a plurality of similar memory cells connected to each half of each bit line. One of the memory cells connected to each line is used as a reference and the other cells are used for data storage. Each half of each bit line is connected to a sense node of a sense amplifier latch through an independently controlled transistor switch. To read the data from the first half of the first bit line, the transistors connecting the first half of the first bit line to the sense node is turned on and the transistor connecting the second half of the first bit line to the sense node is turned off. Both transistor switches connecting respective halves of the other bit line to the other sense node are turned on. Each half of each bit line includes approximately the same effective load. The load applied to the first sense node is thus about half of the load applied to the second sense node.