Abstract: An apparatus 2 for performing serial data communication with a target device 4, such as an integrated circuit, utilizes serial transfer circuitry 16 to perform a serial transfer of data to a communication register 26 in the target device 4 and serial retrieval circuitry 18 to retrieve an acknowledge signal 32 indicating whether or not the target device is ready to perform further processing following such a transfer. Delay control circuitry 20 serves to apply a predetermined delay period following the transfer of the serial data via the serial transfer circuitry before initiating the retrieval of the acknowledge signal. This predetermined delay period is controlled in dependence upon the ready status indicated by the acknowledge signals retrieved such that the proportion of acknowledge signals retrieved which indicate an unready status meets a predetermined condition, such as being less than a non-zero predetermined value.

Abstract: An apparatus 2 for performing serial data communication with a target device 4, such as an integrated circuit, utilizes serial transfer circuitry 16 to perform a serial transfer of data to a communication register 26 in the target device 4 and serial retrieval circuitry 18 to retrieve an acknowledge signal 32 indicating whether or not the target device is ready to perform further processing following such a transfer. Delay control circuitry 20 serves to apply a predetermined delay period following the transfer of the serial data via the serial transfer circuitry before initiating the retrieval of the acknowledge signal. This predetermined delay period is controlled in dependence upon the ready status indicated by the acknowledge signals retrieved such that the proportion of acknowledge signals retrieved which indicate an unready status meets a predetermined condition, such as being less than a non-zero predetermined value.