Patents by Inventor Russell M. dePina

Russell M. dePina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4571724
    Abstract: A functional testing system for programmable logic devices. Test vectors are generated by a shift register and applied to the contact pins of the logic device through isolation elements so that all pins may be treated alike regardless of whether they are inputs or outputs. The logic level on pins that are outputs are controlled by the logic device, while logic levels on pins that are inputs are controlled by the shift register. The response of the logic device to the test vector is recorded in an output shift register and the response is then shifted out of the shift register to one input of an exclusive OR gate that also receives outputs from predetermined stages of the test vector shift register to create a pseudo-random function. The output of the exclusive OR gate is shifted into the test vector shift register as each bit of the logic device's response is applied to the exclusive OR gate thereby creating a new test vector.
    Type: Grant
    Filed: March 23, 1983
    Date of Patent: February 18, 1986
    Assignee: Data I/O Corporation
    Inventors: Victor E. Belmondo, Russell M. dePina, George W. James, Robert G. Martin, John M. Reece