Patents by Inventor Russell Nielsen
Russell Nielsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945579Abstract: A UAV having a manual gimbal including a camera, and a flight mode selector configured to select both a flight mode and manually establish a camera position as a function of the selected fight mode. A controller responds to a position of the gimbal or selector to establish the flight mode. The flight mode is selected from several available modes, for example, a horizontal flight mode, a 45-degree flight mode, and a vertical (aerial) flight mode. The flight mode selector is mechanically coupled to the gimbal and establishes a pitch angle of the gimbal, and thus the camera angle attached to the gimbal.Type: GrantFiled: March 28, 2020Date of Patent: April 2, 2024Assignee: Snap Inc.Inventors: Simon Nielsen, Russell Douglas Patton
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Patent number: 9412594Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: September 16, 2015Date of Patent: August 9, 2016Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Publication number: 20160005601Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: September 16, 2015Publication date: January 7, 2016Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Patent number: 9147608Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: September 15, 2014Date of Patent: September 29, 2015Assignee: MICRON TECHNOLOGY, INC.Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Publication number: 20150004786Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Patent number: 8859362Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: August 8, 2013Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Publication number: 20130320552Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Applicant: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Patent number: 8507341Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: April 12, 2012Date of Patent: August 13, 2013Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
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Publication number: 20120193777Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: April 12, 2012Publication date: August 2, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Luan C. Tran, John Lee, Zengtao "Tony" Liu, Eric Freeman, Russell Nielsen
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Patent number: 8158476Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: August 4, 2010Date of Patent: April 17, 2012Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
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Publication number: 20100317193Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: August 4, 2010Publication date: December 16, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Luan C. Tran, John Lee, Zengtao Tony Liu, Eric Freeman, Russell Nielsen
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Patent number: 7776683Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: May 13, 2008Date of Patent: August 17, 2010Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
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Patent number: 7648919Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: April 20, 2006Date of Patent: January 19, 2010Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
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Patent number: 7611944Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: GrantFiled: August 31, 2005Date of Patent: November 3, 2009Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, John Lee, Zengtao “Tony” Liu, Eric Freeman, Russell Nielsen
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Publication number: 20080227293Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: May 13, 2008Publication date: September 18, 2008Applicant: MICRON TECHNOLOGY, INC.Inventors: Luan C. Tran, John Lee, Zengtao "Tony" Liu, Eric Freeman, Russell Nielsen
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Publication number: 20060216923Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: August 31, 2005Publication date: September 28, 2006Inventors: Luan Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen
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Publication number: 20060216922Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.Type: ApplicationFiled: April 20, 2006Publication date: September 28, 2006Inventors: Luan Tran, John Lee, Zengtao Liu, Eric Freeman, Russell Nielsen