Abstract: An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Abstract: A lock controller supports both blocking and non-blocking lock requests issued by processors of a processing engine when attempting to access a shared resource of an intermediate network device. The non-blocking lock controller capability provides a processor with the flexibility to obtain other shared resources if the originally requested resource is not available. The blocking capability of the lock controller guarantees that each processor will eventually obtain the requested resource. By supporting both blocking and non-blocking capabilities, the lock controller provides increased flexibility and performance to the processors of the processing engine.

Abstract: An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Abstract: A graphics accelerator having first and second processors includes a first vertex breaker unit coupled to the first processor, and a second vertex breaker unit coupled to the second processor. The first breaker unit divides an incoming polygon strip into a first set of substrips, while the second breaker unit divides the incoming polygon strip into a second set of substrips. The graphics accelerator further includes a bus coupled with the first and second breaker units for transmitting the incoming polygon strip to the first breaker unit and the second breaker unit.