Abstract: Systems and methods are disclosed that implement multiple inter-chip (IC) links to communicate digital signals and data between multiple tuner circuit chips of a radio frequency (RF) antenna diversity system. The multiple IC communication links may be employed, for example, to simultaneously communicate different signals and/or data between individual tuner circuit chips of a multi-signal type antenna diversity system in an asynchronous manner, and may be employed to achieve simultaneous antenna diversity for multiple RF signal types using a scalable IC communication link architecture that includes multiple IC communication links to interconnect a varying number of RF tuner circuit chips.

Abstract: A system and method for managing memory is disclosed. The system includes a computer memory array and a memory management unit accessible to the memory array. The memory management unit includes a plurality of parallel comparators. The comparators receive a virtual memory address and perform a comparison of the virtual memory address to a plurality of predetermined addresses. The memory management unit also includes logic responsive to outputs of each of the comparators to determine a physical memory address of an element within the memory array.

Abstract: The disclosure is directed to a computational system including a processor and a memory management unit accessible to the processor. The processor is configured to access a common virtual memory space to perform a first task of a plurality of tasks and is configured to access the common virtual memory space to perform a second task of the plurality of tasks. The common virtual memory space references a first set of instructions associated with the first task and references a second set of instructions associated with the second task. The memory management unit is configured to determine a physical memory location of at least one of the first and second sets of instructions when the associated first or second task is to be performed by the processor.

Abstract: The disclosure is directed to a computational device including functional circuitry, a transceiver interface that is accessible to the functional circuitry, and a universal serial bus transceiver that is accessible to the transceiver interface and that is configured to couple to a universal serial bus compatible media. The transceiver interface is configured to provide a first set of configuration data including a first power setting to a host device via the universal serial bus transceiver. The universal serial bus transceiver is configured to electrically disconnect from and electrically reconnect to the universal serial bus media in response to a suspension signal. The transceiver interface is also configured to provide a second set of configuration data including a second power setting after electrically reconnecting.

Abstract: A semiconductor device includes an adjustable current source that is coupled to an external battery. The semiconductor device includes a feedback control module that is responsive to a voltage level at the external battery. The feedback control module also has an output that is directed to control the current supplied by the adjustable current source. Also, the feedback control module can selectively provide a signal to periodically and temporarily turn off the current supplied by the adjustable current source. A voltage at the external battery is measured during a time period when the current is turned on and during a time period when the current is turned off. While the current is turned off, the feedback control module can measure the external battery voltage so that it can be compared to the battery voltage while the adjustable current source is on.

Abstract: The disclosure is directed to a method of loading a breakpoint enabled page of a computer program into a computer readable memory. The method includes identifying a page of a computer program to be loaded into the computer readable memory and reading a breakpoint table to identify a set of breakpoints having memory addresses located within the page of the computer program prior to loading the page of the computer program. Each breakpoint has an instruction address and an instruction storage location. For each of the set of breakpoints, the method includes reading an operating instruction of the page of the computer program located at the instruction address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table, and loading a trap instruction at the instruction address to replace the operating instruction in the page of the computer program to create a breakpoint enabled page of the computer program.

Abstract: An outage notification system for detecting a power outage at a customer location is provided. The outage notification system comprises a first outage notification device operably coupled to a first circuit at the customer location, a second device operably coupled to a second circuit at the customer location. The first device is operable to determine a status of power supply to the first circuit and communicate the status of power supply to the first circuit to the second device. The second device is operable to determine a status of power supply to the second circuit (or other desired parameter in an alternative embodiment) and notify, via a network, a receiving system associated with the electric utility of a power outage at the customer location based at least in part on the statuses of power supply to the first and/or second circuits.