Abstract: A detector for vertical synchronizing pulses comprises a nonwrapping up/down counter and a comparator. The counter level samples a composite synchronizing signal at a sampling rate. The counter has a numerical output which increases responsive to detection of said level during a sample interval and decreases responsive to nondetection of said level during a sample interval. The comparator generates a vertical sync detection pulse when the numerical output of the counter is greater than a reference value. In order to provide hysteresis, the numerical value os alternately one of first and second numerical reference counts, the first reference count being greater than the second reference count. The comparator initiates the vertical sync detection pulse when the numerical output of the counter rises above the first reference count and terminates the vertical sync detection pulse when the numerical output of the counter falls falls below the second reference count.

Abstract: A clamp circuit includes a coupling capacitor connected between signal input and signal output terminals. A constant current sink and a controlled current source are connected to the output terminal. A comparator, coupled to the output terminal via a lowpass filter, generates signals for conditioning the controlled current source to source current whenever the output terminal exhibits a potential which differs from a predetermined reference in a predetermined polarity sense.

Abstract: A digital signal clamp circuit is realized using an adder and an up/down counter. The digital signal is coupled to one input of the adder and the counter output is coupled to a second input of the adder. The up/down counter is enabled to count only during signal intervals exhibiting the desired clamping level. The counter is controlled to count up or down depending on the polarity of the signal provided by the adder. The count value in the counter is continuously applied to the adder to provide clamping. Using a truncated count value from the counter enhances clamping performance.

Abstract: A picture-in-a-picture television receiver includes a memory for holding samples representing a vertically and horizontally compressed image. The memory is divided into three parts, a main portion which holds one field of the compressed image and first and second crossover buffers, each of which hold one line of the compressed signal. Both upper and lower field types may be derived from each field of the auxiliary signal used to produce the compressed image. Sample values are stored into the memory such that an upper field of the compressed image is stored when an upper field of the main image is displayed and a lower field is stored when a lower field is displayed. When the address used to read samples from the memory overtakes the address used to write samples into the memory, the type of field derived from the auxiliary signal is switched and one line of samples is directed to one of the crossover buffers.

Abstract: A word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance. A second circuit loop loads a multiplicand sample and in response to the clock signal successively divides the multiplicand sample by the factor two. The more significant bits, exclusive of the least significant bit, of the divided multiplicand sample are coupled to a gating circuit. The gating circuit passes the more significant bits to the input of an accumulator if the corresponding bits of the gate signal exhibit a predetermined state. After a number of cycles of the clock signal, corresponding to the number of bits m of the multiplier sample, the accumulator produces a scaled product equal to the muliplicand times the multiplier times the scale factor of 2.sup.-(m-1).

Abstract: A digital D.C. control system includes a multiplexer, a digital-to-analog converter, a capacitor, offset generating circuitry and clamping circuitry. A digital signal to be D.C. controlled and a digital brightness control signal are alternatively coupled by the multiplexer to the input of the digital-to-analog converter. The output from the digital-to-analog converter is coupled to a system output terminal via the capacitor. When the signal is applied to the digital-to-analog converter a fixed D.C. offset is applied to the interconnection of the converter and capacitor. During preselected intervals the D.C. control value is coupled to the digital-to-analog converter concurrently with the system output terminal being clamped to a fixed reference and the D.C. offset circuitry being disabled. This combination of apparatus permits controlling the D.C. level of a digitally processed signal without affecting the dynamic range of the digital signal.

Abstract: A programmable sampled data subsampling system includes a programmable antialias filter which bandlimits the information bandwidth of the signal to be subsampled in accordance with the subsampling rate. The antialias filter includes a recursive filter which scales and combines input samples and delayed combined samples in proportions of K and (1-K) where K is a variable. The variables K are applied to the recursive filter in repeating sequences of N values of K where N is the subsampling factor. Every N.sup.th combined sample is extracted and provided as the subsampled signal.

Abstract: A phase locking system for providing a sampling signal which is to be phase/frequency locked to an applied signal includes a controllable oscillator coupled to a sampling circuit to produce samples of the applied signal representing substantially quadrature phase related components of the applied signal. An accumulator respectively accumulates the quadrature phase components over predetermined intervals. A differencing circuit successively forms the differences of one of the components from successive intervals. The differences are used to generate a control signal to alter the signal generated by the controllable oscillator.

Abstract: A signal combining circuit for adaptively combining first and second signals includes a comparator to develop a control signal to indicate when the combination of the first and second signals will have an amplitude exceeding a predetermined amplitude in one polarity sense. In the absence of the control signal the first and second signals are combined. On the occurrence of the control signal the first signal is combined with a further signal related to the first signal and a reference value.

Abstract: A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator for producing a signal having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit which is reset once every horizontal line. In accordance with another aspect of this invention, the state of the divide-by-K circuit is captured and saved for use in a chroma demodulation apparatus just before it is reset.

Abstract: A secondary video signal is sampled, digitized and combined with an in-memory switching signal. The combined digital signal is stored in a random access video memory. The stored signal is read out in synchronism with the synchronizing signal components of a primary video signal. The switching signal is recovered from the output of the memory, and compared with a content code signal to develop a fast switching signal. A video output switch, coupled to receive the primary video signal and the stored secondary video signal and responsive to the fast switching signal, applies an appropriate one of the two input signals to the kinescope to define a secondary inset picture within a large primary picture.

Abstract: An apparatus is disclosed for generating a burst-locked, color subcarrier representative signal .phi..sub.sc from a skew-corrected clock signal MCS (which is reset once every horizontal line) and a skew error signal SES (indicative of the once-a-line phase adjustment of the skew-corrected clock signal). In accordance with another feature of the invention, a chroma demodulation apparatus is provided for generating a pair of color difference signals R-Y and B-Y in response to the internally-generated .phi..sub.sc signal.

Abstract: A scaling circuit for scaling PCM signals by factors less than one includes a bit-shift and truncating circuit. Roundoff error compensating circuitry adds an offset value to the samples to be scaled by the bit-shift circuitry to compensate for errors produced by truncation without rounding. The offset values are dithered to increase the apparent resolution of the system.

Abstract: A memory-based television receiver includes an apparatus for generating a composite sync signal CSS for timing the memory reading operation and the deflection circuits of the receiver. The horizontal sync components of the internally-generated composite sync signal are locked to the system clock. The vertical sync components of the internally-generated composite sync signal are, on the other hand, locked to the vertical sync components of the incoming video signal.

Abstract: A picture-in-picture television receiver for which the viewer may change the size of the inset image includes an adaptive anti-aliasing filter. Composite video signals which produce the inset image are applied to a separation filter which attenuates the chrominance components to provide separated luminance signals. The luminance signals are applied to a second filter which includes a variable delay element and an adder. The luminance signals are applied to one input port of the adder and to the delay element. The signals provided by the delay element are applied to the second input port of the adder. The delay element provides time delays which may be expressed by the equation T=K.sub.2 .tau.+PK.sub.1 .tau. where .tau. is a fixed amount of time, K.sub.1 and K.sub.2 are constants and P is a variable. The frequency response characteristic of the filter is changed by changing the value of P.

Abstract: An angle .alpha. from 0.degree. to 45.degree. is determined from an equation .alpha..degree.=LK.iota.(tan .alpha.).sup..iota., where .iota. is an index varying from 0 to n. The value of tan .alpha. is arrived at by dividing the smaller of the I,Q magnitude values by the larger of the two magnitude values. The angle .alpha. from 0.degree. to 45.degree. is transposed to the corresponding phase angle .theta. of the vector sum C of the orthogonal I,Q signals over the full range of values from 0.degree. to 360.degree..

Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.

Abstract: In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to have jittering time bases that generally have prevented the use of such memory-based processing systems. The jittering signals may be standardized, in sampled data format, by effecting adaptive signal delays responsive to a measure of the relative phase of the sampling clock with respect to horizontal synchronizing pulses. The phase measure is used to control an interpolator which combines successive samples in proportions to develop sample values that should have occurred at the sample times had the signal not been jittering.

Abstract: A television receiver is arranged to selectively display images from several input signal sources--such as pix-in-pix, teletext, computer graphics, besides displaying pictures from the normal off-the-air television signal. In accordance with this invention, clamping circuits are provided for establishing a constant black image reference level for all the input signals.

Abstract: A pix-in-pix television display includes a memory for holding samples representing one field of the small picture. Samples which are to be written into the memory are developed in a buffer memory one line at a time over intervals corresponding to the three line periods of the signal which produces the small picture. A line of samples is written from the buffer memory into the field memory over three line periods of the small picture signal. The memory write operation is suspended when data is read from the field memory for display. The write operation resumes when a read operation is completed at the address and pixel value which were being written when the write operation was suspended.