Abstract: A method and apparatus providing computer system cryptographic protection including a processor, a trusted platform module, trusted bus devices, a first secure memory and a second secure memory, wherein the first and second memory each have a first and second shadow copy, an external bus controller, and a system bus. The system bus contains trusted data and connects with the processor, the trusted platform module, trusted bus devices, the first and second secure memory and the external bus controller. The first and second secure memory separating code and data via physically distinct memory components. The contents of the distinct memory components being replicated into two shadow copies for each component, wherein during a write operation, simultaneously updating the shadow copies with the contents of the distinct components, and during a read operation, sending the two shadow copies and the memory component to a majority function.

Abstract: A method and apparatus providing computer system cryptographic protection including a processor, a trusted platform module, trusted bus devices, a first secure memory and a second secure memory, wherein the first and second memory each have a first and second shadow copy, an external bus controller, and a system bus. The system bus contains trusted data and connects with the processor, the trusted platform module, trusted bus devices, the first and second secure memory and the external bus controller. The first and second secure memory separating code and data via physically distinct memory components. The contents of the distinct memory components being replicated into two shadow copies for each component, wherein during a write operation, simultaneously updating the shadow copies with the contents of the distinct components, and during a read operation, sending the two shadow copies and the memory component to a majority function.