Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to adjust vias in integrated circuits (ICs) based on machine learning (ML). An example apparatus computes a dimension by which to extend a via based on at least one of a first metal wire in a first layer of the IC above the via, a via-to-via patterning constraint, or a via-to-metal shorting constraint for a second layer of the IC below the via. The example apparatus also computes a shifted position of the via based on at least one of (a) the dimension or (b) a width and a position of a second metal wire below the via, the width and the position predicted by an ML model. Additionally, the example apparatus adjusts a configuration file corresponding to the IC based on at least one of the dimension or the shifted position of the via.