Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: An image sensor may include an array of imaging pixels. Each imaging pixel may have a photodiode that generates charge in response to incident light, a floating diffusion region, and a transfer transistor that transfers charge from the photodiode to the floating diffusion region. Each floating diffusion region may have an associated capacitance formed by a depletion region between n-type and p-type regions in a semiconductor substrate. To enable selective binning in the voltage domain, a number of transistors may be coupled to the floating diffusion capacitors. A first plurality of pixels may selectively couple the floating diffusion capacitors to ground. A second plurality of pixels may selective couple the floating diffusion capacitors to the floating diffusion capacitors of adjacent pixels. The voltages of multiple floating diffusion capacitors may be non-destructively binned on a single floating diffusion capacitor during readout.

Abstract: An image sensor may include an array of imaging pixels. Each imaging pixel may have a photodiode that generates charge in response to incident light, a floating diffusion region, and a transfer transistor that transfers charge from the photodiode to the floating diffusion region. Each floating diffusion region may have an associated capacitance formed by a depletion region between n-type and p-type regions in a semiconductor substrate. To enable selective binning in the voltage domain, a number of transistors may be coupled to the floating diffusion capacitors. A first plurality of pixels may selectively couple the floating diffusion capacitors to ground. A second plurality of pixels may selective couple the floating diffusion capacitors to the floating diffusion capacitors of adjacent pixels. The voltages of multiple floating diffusion capacitors may be non-destructively binned on a single floating diffusion capacitor during readout.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.