Patents by Inventor Ruth A. Brain
Ruth A. Brain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190363008Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.Type: ApplicationFiled: December 23, 2016Publication date: November 28, 2019Inventors: Florian GSTREIN, Eungnak HAN, Rami HOURANI, Ruth A. BRAIN, Paul A. NYHUS, Manish CHANDHOK, Charles H. WALLACE, Chi-Hwa TSANG
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Patent number: 10468298Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.Type: GrantFiled: January 16, 2019Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri, Ruth A. Brain
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Publication number: 20190221478Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.Type: ApplicationFiled: January 16, 2019Publication date: July 18, 2019Inventors: Yuriy V. SHUSTERMAN, Flavio GRIGGIO, Tejaswi K. INDUKURI, Ruth A. BRAIN
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Publication number: 20190206728Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.Type: ApplicationFiled: September 30, 2016Publication date: July 4, 2019Inventors: Charles H. WALLACE, Marvin Y. PAIK, Hyunsoo PARK, Mohit K. HARAN, Alexander F. KAPLAN, Ruth A. BRAIN
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Publication number: 20190164818Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.Type: ApplicationFiled: December 30, 2017Publication date: May 30, 2019Inventors: Andrew W. YEOH, Ruth BRAIN, Michael L. HATTENDORF, Christopher P. AUTH
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Publication number: 20190122982Abstract: An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.Type: ApplicationFiled: June 22, 2016Publication date: April 25, 2019Inventors: Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain, Mark T. Bohr, Manish Chandhok
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Publication number: 20190081233Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.Type: ApplicationFiled: April 1, 2016Publication date: March 14, 2019Applicant: INTEL CORPORATIONInventors: KEVIN J. LEE, OLEG GOLONZKA, TAHIR GHANI, RUTH A. BRAIN, YIH WANG
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Patent number: 10211098Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.Type: GrantFiled: June 11, 2018Date of Patent: February 19, 2019Assignee: Intel CorporationInventors: Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri, Ruth A. Brain
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Publication number: 20190013353Abstract: Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.Type: ApplicationFiled: March 7, 2016Publication date: January 10, 2019Inventors: Kevin J. LEE, Oleg GOLONZKA, Tahir GHANI, Ruth A. BRAIN, Yih WANG
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Publication number: 20180350672Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.Type: ApplicationFiled: June 11, 2018Publication date: December 6, 2018Applicant: INTEL CORPORATIONInventors: YURIY V. SHUSTERMAN, FLAVIO GRIGGIO, TEJASWI K. INDUKURI, RUTH A. BRAIN
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Patent number: 10032857Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.Type: GrantFiled: February 8, 2017Date of Patent: July 24, 2018Assignee: Intel CorporationInventor: Ruth A. Brain
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Patent number: 10032643Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.Type: GrantFiled: December 22, 2014Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Jasmeet S. Chawla, Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers
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Patent number: 10026649Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.Type: GrantFiled: December 23, 2014Date of Patent: July 17, 2018Assignee: INTEL CORPORATIONInventors: Yuriy V. Shusterman, Flavio Griggio, Tejaswi K. Indukuri, Ruth A. Brain
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Publication number: 20180174893Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.Type: ApplicationFiled: February 18, 2018Publication date: June 21, 2018Applicant: INTEL CORPORATIONInventors: RAMI HOURANI, MARIE KRYSAK, FLORIAN GSTREIN, RUTH A. BRAIN, MARK T. BOHR
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Publication number: 20180122744Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: ApplicationFiled: October 2, 2017Publication date: May 3, 2018Inventors: Ruth A. BRAIN, Kevin J. FISCHER, Michael A. CHILDS
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Patent number: 9899255Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.Type: GrantFiled: December 23, 2014Date of Patent: February 20, 2018Assignee: INTEL CORPORATIONInventors: Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain, Mark T. Bohr
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Publication number: 20170338148Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.Type: ApplicationFiled: December 23, 2014Publication date: November 23, 2017Applicant: INTEL CORPORATIONInventors: YURIY V. SHUSTERMAN, FLAVIO GRIGGIO, TEJASWI K. INDUKURI, RUTH A. BRAIN
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Publication number: 20170330794Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.Type: ApplicationFiled: December 23, 2014Publication date: November 16, 2017Applicant: INTEL CORPORATIONInventors: RAMI HOURANI, MARIE KRYSAK, FLORIAN GSTREIN, RUTH A. BRAIN, MARK T. BOHR
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Publication number: 20170330761Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.Type: ApplicationFiled: December 22, 2014Publication date: November 16, 2017Inventors: Jasmeet S. CHAWLA, Ruth A. BRAIN, Richard E. SCHENKER, Kanwal Jit SINGH, Alan M. MEYERS
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Patent number: 9780038Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: GrantFiled: October 24, 2016Date of Patent: October 3, 2017Assignee: Intel CorporationInventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs