Abstract: A two part insole having one part for housing smart systems embedded within an insole, and a second part for maintaining comfort of a cut-to-fit insole to increase the functionality of the overall product for the user.

Abstract: An energy generation and storage system includes an energy generation device within a component of a shoe. The system also includes an energy storage device having an attachment structure configured to removably secure the energy storage device to the shoe or the shoe's wearer and electrically connect to the energy generation device via a power cord.

Abstract: An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test.

Abstract: An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test.