Patents by Inventor Rutul BHATT

Rutul BHATT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10853282
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 1, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Rutul Bhatt
  • Patent number: 10838891
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Rutul Bhatt
  • Publication number: 20190303325
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Rutul BHATT
  • Publication number: 20190303326
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Rutul BHATT