Patents by Inventor Ruwantha JAYASINGHA

Ruwantha JAYASINGHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260182013
    Abstract: Gate-all-around integrated circuit structures having gate dielectrics with differentiated transition layer thickness are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires or fin and a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, where the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a transition layer comprising silicon and oxygen and having a first thickness. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, where the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a transition layer comprising silicon and oxygen and having a second thickness greater than the first thickness.
    Type: Application
    Filed: December 24, 2024
    Publication date: June 25, 2026
    Inventors: Yang CAO, David J. TOWNER, Jubin NATHAWAT, Ruwantha JAYASINGHA, Petr NOVOTNY, Rahul RAMAMURTHY, Daniel JARAMILLO CABANZO, Yihao FANG, Michael L. HATTENDORF, Sridhar GOVINDARAJU, Kiran CHIKKADI