Abstract: An image synthesis process includes generating a target defect patch using a source image that displays a defect and a corresponding segmentation mask. A noisy latent representation is generated based on a latent representation of an input image via a forward diffusion process. A synthetic image is generated by decoding a new latent representation. The new latent representation is generated via a reverse diffusion process involving steps. Each step includes (i) generating an optimized iterate of a current version of denoising the noisy latent representation by minimizing an energy function that compares differences between (a) a current segment patch that is a cropping of the segmentation mask overlayed on a current clean image, and (b) the target defect patch; (ii) predicting a current noise amount of the optimized iterate; and (iii) generating a next version using the current noise amount and the optimized iterate.

Abstract: A computer-implemented method generates a synthetic image with a blended defect, combining a first and second defect. A target feature map is created by merging masked feature maps derived from source images displaying the respective defects. These feature maps are generated using a machine learning model during a forward diffusion process. A noisy latent representation is obtained from an input image via another forward diffusion process. A new latent representation is then created through reverse diffusion, involving: (i) minimizing an energy function that compares a masked current feature map with the target feature map, (ii) predicting noise in the current iteration via the machine learning model, and (iii) updating the latent representation. The final synthetic image is produced by decoding the updated latent representation.

Abstract: Methods for fine-tuning a convolutional neural network of a Text-To-Image Diffusion Model within a context of recognizing defects of manufactured products within images of those products are disclosed. Images of manufactured images that have various scratches, dents, or other defects are provided to the model along with a word or phrase indicating that there is a defect. The model then learns to identify the portion of the overall image that includes the defect. The learning of this type of task is based on the use of segmentation masks that correspond to the images, which are then used along with cross-attention maps of the model in order to calculate an average defect mask loss parameter of the model. By computing this parameter and applying it when updating weights of the model, the model can be fine-tuned to detect defects of manufactured products.

Abstract: A computer-implemented method relates to generating a synthetic image with a new defect via reverse diffusion process that includes background disentanglement via a feature-based optimization process at every step. The method includes generating a background image by erasing a source defect from a source image. The source defect itself is extracted from the source image by subtracting the background image from the source image. The source defect is combined with a background of an input image. The synthetic image displays the new defect on the background of the input image instead of the background of the source image.

Abstract: An image synthesis process includes generating a target mask based on a segmentation mask of a defect displayed in a source image. A source feature map is generated based on the source image at each step of a forward diffusion process. A synthetic image is generated via a reverse diffusion process involving steps. Each step includes (i) generating an optimized iterate of a latent representation of a current version of denoising a latent representation of a noisy input image by minimizing an energy function that compares differences between (a) a current feature map generated based on the latent representation of the current version and (b) a target feature map generated using the target mask and the source feature map (ii) predicting a current noise amount of the optimized iterate, and (iii) generating a latent representation of a next version using the current noise amount and the optimized iterate.

Abstract: A semiconductor device includes a substrate and a first active area in the substrate, wherein the first active area is configured to facilitate a first leakage less than a predetermined threshold. The semiconductor device includes a second active area in the substrate, wherein the second active area is configured to facilitate a second leakage. The semiconductor device includes a third active area in the substrate, wherein the third active area is configured to facilitate a third leakage equal to or greater than the predetermined threshold. The semiconductor device includes a first gate structure extending over each of the first active area, the second active area and the third active area; a second gate structure over the first active area; and a third gate structure over the second active area. The semiconductor device includes an isolation dummy gate between and aligned with the second gate structure and the third gate structure.

Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

Abstract: A memory device includes a first word line and a second word line. The first word line is configured to transmit a first word line signal to a first set of memory cells. A first portion of the first word line is formed in a first metal layer, and a second portion of the first word line is formed in a second metal layer above the first metal layer. The second word line is configured to transmit a second word line signal to a second set of memory cells. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The second portion of the first word line is partially overlapped with the second portion of the second word line.

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.

Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.

Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.