Abstract: The present application discloses a DQN-based distributed computing network coordinate flow scheduling system and method.

Abstract: The disclosure discloses a mimetic database-based network operating system design method, including: designing a mimetic data structure; designing a mimetic data object; designing a synchronization mechanism and a decision mechanism, designing a mimetic database safe storage command processing system, and designing a classification storage mechanism for interacting data between service modules and a master database in a network operating system. By means of vertical hierarchy and horizontal classification, the problem of compatibility of the database subjected to mimetic transformation and a network operating system is solved. By means of a memory random distribution storage mechanism and a memory hardware heterogeneous storage mechanism, the cost caused by mimetic transformation can be reduced, and the cost is controllable while the safety is improved.

Abstract: The present disclosure discloses a compiling system for a compiling system and a compiling method for a programmable network element.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: The present disclosure discloses a reinforcement learning agent training method, modal bandwidth resource scheduling method and apparatus. The reinforcement learning agent training method utilizes a reinforcement learning agent to continuously interact with a network environment in a polymorphic smart network to obtain the latest global network characteristics and output updated actions. By adjusting the bandwidth occupied by modals, a reward value is set to determine an optimization target for the agent, the scheduling of modals is realized, and the rational use of polymorphic smart network resources is guaranteed. The trained reinforcement learning agent is applied to the modal bandwidth resource scheduling method, and can adapt to networks with different characteristics, and thus can be used for intelligent management and control of polymorphic smart networks and has good adaptability and scheduling performance.

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.

Abstract: A content store-and-forward method, apparatus, an electronic apparatus and a storage medium, the method comprising the following steps: receiving an interest packet in a named data network; forwarding the interest packet to a storage node, so that the storage node looks up the corresponding content, and packages the content into a data packet containing the hash value of the name identifier and the corresponding content; receiving the data packet forwarded by the storage node; forwarding the data packet to an interest packet port, wherein the interest packet port is a port that has once received the name identifier corresponding to the content in the data packet; forwarding another data packet to the storage node, so that the storage node parses the hash value and the content of the name identifier in the another data packet, and stores the hash value of the name identifier and the corresponding content.

Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.

Abstract: A method and an apparatus for screening TB-scale of incremental data. In the present application, according to the memory capacity of the device, the raw data is divided into a plurality of raw data blocks, and the data is cleaned. By adopting a single-block index sorting algorithm, the de-duplicating ordering in the data blocks is completed without dropping operation, and the processed data blocks and a matrix hash index table are respectively generated and saved as initial data after completion. For the subsequent incremental data, the inter-block index-sorting algorithm is adopted, and the processed data blocks and the matrix hash index table are loaded in turn. The data is preliminarily screened on the basis of the matrix hash index table, and an incremental binary search algorithm is used for fine screening. Finally, the indexing and de-duplication screening of all data are completed.

Abstract: The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.

Abstract: A service processing method includes that a first network device determines a second network device on a forwarding path of a packet based on a service requirement; the first network device sends a first message to the second network device, to establish a first connection to the second network device; and the first network device sends a second message to the second network device using the first connection, where the second message requests the second network device to assist in determining information related to the forwarding path. when determining the second network device is needed to assist the first network device for information related to the forwarding path of the packet, the first network device actively establishes a connection to the second network device, and requests, using the established connection, the second network device to assist the first network device in determining the information related to the forwarding path.

Abstract: A software and hardware collaborative compilation processing method and system. The system comprises an environment configurator, a command parser, a code filler, a scheduler and a heterogeneous target system, wherein the code filler is configured for obtaining the source program path of a user, reading source codes and identifying the heterogeneous target system according to a macro definition, complementing the codes related to the heterogeneous target system, carrying out primary filling and secondary filling on the source codes; the scheduler is configured for realizing compilation scheduling and execution scheduling functions respectively; the heterogeneous target system is configured for compiling and processing user modal data, and comprises at least two heterogeneous target subsystems; each target subsystem comprises a target-related middle-end compiler, a back-end compiler and a target-related running environment.

Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.

Abstract: The disclosure discloses a mimetic database-based network operating system design method, including: designing a mimetic data structure; designing a mimetic data object; designing a synchronization mechanism and a decision mechanism, designing a mimetic database safe storage command processing system, and designing a classification storage mechanism for interacting data between service modules and a master database in a network operating system. By means of vertical hierarchy and horizontal classification, the problem of compatibility of the database subjected to mimetic transformation and a network operating system is solved. By means of a memory random distribution storage mechanism and a memory hardware heterogeneous storage mechanism, the cost caused by mimetic transformation can be reduced, and the cost is controllable while the safety is improved.

Abstract: The present invention relates to the technical field of network communication, in particular to a method and system for controlling ID identifier network mobility based on a programmable switch. The system includes mobile terminal nodes, mobile access points, programmable switching nodes and control nodes, wherein the control nodes include local control nodes and a global control node, the mobile terminal nodes are connected and communicated with the mobile access points through wireless data links, the mobile access points are connected and communicated with the programmable switching nodes through wired data links, and the programmable switching nodes, the local control nodes and the global control node are connected and communicated in order through control links.