Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: A differential-follower control circuit has been provided, comprising: a follower; an output-voltage following module, which controls a voltage at a control terminal of the follower to vary with an output voltage; a substrate-voltage following module, which controls a substrate voltage of an output transistor of the follower to vary with an input voltage; an output terminal of the follower is connected to a first terminal of the output-voltage following module; a second terminal of the output-voltage following module is connected to the control terminal of the follower; a first terminal of the substrate-voltage following module is connected to an input terminal of the follower and a second terminal of the substrate-voltage following module is connected to a substrate of the output transistor; the invention effectively improves the overall linearity of the follower.

Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.

Abstract: A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

Abstract: A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.

Abstract: The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates.

Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor MO that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.

Abstract: The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates.

Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.

Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.

Abstract: The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result.

Abstract: The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result.

Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.