Patents by Inventor Ryan A. Fitch
Ryan A. Fitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210227865Abstract: An edible composition, comprising a low glycemic index sugar component having a glycemic index of not more than 20, wherein the edible composition comprises not less than 50% weight of the low glycemic index sugar component, wherein the edible composition is substantially free of D-sucrose, D-fructose, D-glucose, sugar alcohols, and non-sugar sweeteners, and wherein the edible composition have a sweetness taste profile substantially similar to D-sucrose.Type: ApplicationFiled: June 13, 2019Publication date: July 29, 2021Inventors: Feng Wan, William Carlson, Bradley Ryan FITCH, Kathy LYNN, Christopher David BAILEY
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Patent number: 9746516Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.Type: GrantFiled: April 27, 2016Date of Patent: August 29, 2017Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
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Patent number: 9568549Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.Type: GrantFiled: August 11, 2015Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Publication number: 20160238656Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.Type: ApplicationFiled: April 27, 2016Publication date: August 18, 2016Inventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
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Patent number: 9372232Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches data source. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. A related latches table may be created by tracing from a target latch.Type: GrantFiled: December 16, 2013Date of Patent: June 21, 2016Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
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Patent number: 9366723Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.Type: GrantFiled: July 11, 2014Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9285423Abstract: A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.Type: GrantFiled: December 16, 2013Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
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Publication number: 20150346279Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9201117Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.Type: GrantFiled: May 6, 2013Date of Patent: December 1, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9188636Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.Type: GrantFiled: December 6, 2012Date of Patent: November 17, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9116205Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).Type: GrantFiled: September 27, 2012Date of Patent: August 25, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9103879Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).Type: GrantFiled: February 27, 2013Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 9069041Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.Type: GrantFiled: December 5, 2012Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Publication number: 20150168490Abstract: A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
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Publication number: 20150168491Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches data source. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. A related latches table may be created by tracing from a target latch.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
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Patent number: 9032256Abstract: Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores.Type: GrantFiled: January 11, 2013Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Dennis M. Rickert
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Patent number: 9003244Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.Type: GrantFiled: July 31, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Publication number: 20150039957Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Patent number: 8898530Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.Type: GrantFiled: October 23, 2013Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
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Publication number: 20140331097Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.Type: ApplicationFiled: May 6, 2013Publication date: November 6, 2014Applicant: International Business Machines CorporationInventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer