Patents by Inventor Ryan A. MacDonald
Ryan A. MacDonald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230195980Abstract: Systems and methods are disclosed for integrated circuit design using integrated circuit shells. For example, a system may generate an integrated circuit core design expressed in a hardware description language. The integrated circuit core design may express circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC). The one or more functions may have connection points providing first inputs and outputs to the one or more functions. The system may query an integrated circuit shell expressed in a hardware description language. The integrated circuit shell may express circuitry that describes a limited set of pads to be implemented in the ASIC. The limited set of pads may provide second inputs and outputs to the integrated circuit. The query may determine availability of pads of the limited set of pads to connect to the connection points of the one or more functions.Type: ApplicationFiled: November 23, 2022Publication date: June 22, 2023Inventors: Ryan Macdonald, Erik Arthur Daine, Wesley Waylon Terpstra, Yunsup Lee
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Patent number: 11675945Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: May 2, 2022Date of Patent: June 13, 2023Assignee: SiFive, Inc.Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Publication number: 20220261522Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Patent number: 11321511Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: January 25, 2021Date of Patent: May 3, 2022Assignee: SiFive, Inc.Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Patent number: 11313693Abstract: A system for closest in path vehicle following using surrounding vehicles motion flow is provided and includes a sensor device of a host vehicle generating data related to vehicles upon a drivable surface. The system further includes a navigation controller including a computerized processor operable to monitor the data from the sensor device, define a portion of the plurality of vehicles as a swarm of vehicles, identify one of the plurality of vehicles as a closest in path vehicle to be followed, evaluate the data to determine whether the closest in path vehicle to be followed is exhibiting good behavior in relation to the swarm of vehicles, and, when the closest in path vehicle to be followed is exhibiting the good behavior, generate a breadcrumbing navigation path based upon the data. The system further includes a vehicle controller controlling the host vehicle based upon the breadcrumbing navigation path.Type: GrantFiled: March 3, 2020Date of Patent: April 26, 2022Assignee: GM Global Technology Operations LLCInventors: Ryan A. MacDonald, Mohammadali Shahriari, Dorothy Lui, Donovan J. Wisner, Benjamin J. Gaffney
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Publication number: 20210278231Abstract: A system for closest in path vehicle following using surrounding vehicles motion flow is provided and includes a sensor device of a host vehicle generating data related to vehicles upon a drivable surface. The system further includes a navigation controller including a computerized processor operable to monitor the data from the sensor device, define a portion of the plurality of vehicles as a swarm of vehicles, identify one of the plurality of vehicles as a closest in path vehicle to be followed, evaluate the data to determine whether the closest in path vehicle to be followed is exhibiting good behavior in relation to the swarm of vehicles, and, when the closest in path vehicle to be followed is exhibiting the good behavior, generate a breadcrumbing navigation path based upon the data. The system further includes a vehicle controller controlling the host vehicle based upon the breadcrumbing navigation path.Type: ApplicationFiled: March 3, 2020Publication date: September 9, 2021Applicant: GM Global Technology Operations LLCInventors: Ryan A. MacDonald, Mohammadali Shahriari, Dorothy Lui, Donovan J. Wisner, Benjamin J. Gaffney
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Publication number: 20210173987Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: January 25, 2021Publication date: June 10, 2021Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Publication number: 20210124360Abstract: A system for closest in path vehicle following is provided. The system includes a sensor device of a vehicle to be controlled generating data related to a closest in path vehicle and related to a drivable surface in front of the vehicle. The system further includes a navigation control module including a computerized processor operable to monitor the data from the sensor device, evaluate the data to determine a quality measure of a path followed by the closest in path vehicle, and if the quality measure of the closest in path vehicle is above a high-quality candidate threshold, generate a breadcrumbing navigation path based upon the data. The system further includes a vehicle control module controlling the vehicle to be controlled based upon the breadcrumbing navigation path.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Ryan A. MacDonald, Mohammadali Shahriari, Dorothy Lui, Donovan J. Wisner
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Patent number: 10902171Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: July 9, 2019Date of Patent: January 26, 2021Assignee: SiFive, Inc.Inventors: Henry Cook, Wesley Waylon Terpstra, Ryan Macdonald
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Publication number: 20210011981Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: July 9, 2019Publication date: January 14, 2021Inventors: Henry Cook, Wesley Waylon Terpstra, Ryan MacDonald