Abstract: A receiver circuit for detecting and waking up to a wakeup impulse sequence is provided. Herein, a transmitter circuit is configured to transmit a wakeup impulse sequence to wake up a receiver circuit. The receiver circuit includes a main receiver circuit and a wakeup receiver circuit. The main receiver circuit, which consumes far more energy than the wakeup receiver circuit, will remain in sleep mode as much as possible to conserve power. While the main receiver circuit is asleep, the wakeup receiver circuit is configured to detect the wakeup impulse sequence and wake up the main receiver circuit if the wakeup impulse sequence is intended for the receiver circuit. By keeping the main receiver circuit asleep as much as possible, it is possible to reduce power consumption, thus making the receiver circuit an ideal receiver option for an Internet-of-Things (IoT) device(s).

Abstract: A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.

Abstract: An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

Abstract: A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.

Abstract: A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

Abstract: An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

Abstract: An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer. During coarse tuning, a reference signal used to control an output frequency of the PLL is provided to the coarse tuning circuitry and is divided by a factor M to provide a divided reference signal. A controllable oscillator (CO) output signal from a CO in the PLL is divided by an N divider in the PLL to provide a divided CO signal. The periods or, equivalently, frequencies of the divided CO signal and the divided reference signal are compared, and the result is used to select an appropriate tuning curve for the CO. In order to reduce a period comparison error, synchronization circuitry operates to synchronize the N divider of the PLL and an M divider of the coarse tuning circuit.