Abstract: A system and process for upgrading a hydrocarbon-based composition, that includes introducing the hydrocarbon-based composition into a reaction zone heated with electricity, concentrated solar radiation heat, nuclear reactor heat, geothermal heat, molten salt, molten metal, or combinations thereof; heating the hydrocarbon-based composition in the reaction zone to create a product stream; cooling the product stream create a cooled product stream, wherein: the reaction zone does not produce flue gas.

Abstract: Embodiments of the disclosure provide for managing data stored in memory of a device. Maintaining variable-sized data records in an Internet-of-Things (IoT) device can comprise receiving data for a new record to be stored in a memory of the IoT device and searching data frames stored in the memory of the IoT device. The data frames can be stored in the memory of the IoT device in a circular manner and each data frame can store therein a data record of variable size. Searching the data frames can comprise locating a head data frame and a tail data frame. Each data frame can be validated during the searching of the plurality of data frames. In response to locating a valid tail data frame, the data for the new record can be written into a new tail frame for the plurality of data frames.

Abstract: A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.

Abstract: A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.

Abstract: This document discusses high speed data communication systems and methods, such as for communicating symbols using pulse-amplitude-modulated (PAM) or other multilevel (i.e., more than two) signal levels (e.g., PAM5 symbols using five signal levels). One example encodes and/or decodes between n-bit blocks of binary data (e.g., n=12) and m-symbol code words (e.g., m=6 PAM5 symbols). In this example, the code words are selected to limit the runlength of consecutive symbols transmitted without a symmetric-about-baseline transition between signal levels. In another example, the code words bound a word disparity representing a cumulative deviation from baseline of the values of the symbols of the code words. In a further example, the code words bound an intraword disparity representing a symbol-by-symbol cumulative deviation from baseline, within the code word.